r600g: rework scissor for r600-r700

[mesa.git] / src / gallium / drivers / r600 / r600_state.c

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 806d7dd4b35d85619d811d6e956b28314318ed78..163469c0c6424e219dba33225cd4b95d035cdc19 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -772,7 +772,6 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
        struct r600_pipe_state *rstate;
        unsigned tmp;
        unsigned prov_vtx = 1, polygon_dual_mode;
-       unsigned clip_rule;
        unsigned sc_mode_cntl;
        float psize_min, psize_max;
 
@@ -800,7 +799,6 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
                S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
                S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 
-       clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
        /* offset */
        rs->offset_units = state->offset_units;
        rs->offset_scale = state->offset_scale * 12.0f;
@@ -840,10 +838,18 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
        tmp = (unsigned)state->line_width * 8;
        r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
 
-       if (rctx->chip_class >= R700)
-               sc_mode_cntl = 0x514002;
-       else
-               sc_mode_cntl = 0x4102;
+       if (rctx->chip_class >= R700) {
+               sc_mode_cntl =
+                       S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
+                       S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
+                       S_028A4C_R700_ZMM_LINE_OFFSET(1) |
+                       S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
+       } else {
+               sc_mode_cntl =
+                       S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
+                       S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
+               rs->scissor_enable = state->scissor;
+       }
        sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
        
        r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl,
@@ -854,7 +860,6 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
                                NULL, 0);
 
        r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
-       r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
        r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
                                S_028814_PROVOKING_VTX_LAST(prov_vtx) |
                                S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
@@ -1254,10 +1259,9 @@ static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask
 {
 }
 
-static void r600_set_scissor_state(struct pipe_context *ctx,
-                                       const struct pipe_scissor_state *state)
+void r600_set_scissor_state(struct r600_context *rctx,
+                           const struct pipe_scissor_state *state)
 {
-       struct r600_context *rctx = (struct r600_context *)ctx;
        struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
        uint32_t tl, br;
 
@@ -1268,28 +1272,10 @@ static void r600_set_scissor_state(struct pipe_context *ctx,
        tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
        br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
        r600_pipe_state_add_reg(rstate,
-                               R_028210_PA_SC_CLIPRECT_0_TL, tl,
-                               NULL, 0);
-       r600_pipe_state_add_reg(rstate,
-                               R_028214_PA_SC_CLIPRECT_0_BR, br,
-                               NULL, 0);
-       r600_pipe_state_add_reg(rstate,
-                               R_028218_PA_SC_CLIPRECT_1_TL, tl,
-                               NULL, 0);
-       r600_pipe_state_add_reg(rstate,
-                               R_02821C_PA_SC_CLIPRECT_1_BR, br,
-                               NULL, 0);
-       r600_pipe_state_add_reg(rstate,
-                               R_028220_PA_SC_CLIPRECT_2_TL, tl,
-                               NULL, 0);
-       r600_pipe_state_add_reg(rstate,
-                               R_028224_PA_SC_CLIPRECT_2_BR, br,
-                               NULL, 0);
-       r600_pipe_state_add_reg(rstate,
-                               R_028228_PA_SC_CLIPRECT_3_TL, tl,
+                               R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
                                NULL, 0);
        r600_pipe_state_add_reg(rstate,
-                               R_02822C_PA_SC_CLIPRECT_3_BR, br,
+                               R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
                                NULL, 0);
 
        free(rctx->states[R600_PIPE_STATE_SCISSOR]);
@@ -1297,6 +1283,21 @@ static void r600_set_scissor_state(struct pipe_context *ctx,
        r600_context_pipe_state_set(rctx, rstate);
 }
 
+static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
+                                       const struct pipe_scissor_state *state)
+{
+       struct r600_context *rctx = (struct r600_context *)ctx;
+
+       if (rctx->chip_class == R600) {
+               rctx->scissor_state = *state;
+
+               if (!rctx->scissor_enable)
+                       return;
+       }
+
+       r600_set_scissor_state(rctx, state);
+}
+
 static void r600_set_viewport_state(struct pipe_context *ctx,
                                        const struct pipe_viewport_state *state)
 {
@@ -1621,12 +1622,6 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
        r600_pipe_state_add_reg(rstate,
                                R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
                                NULL, 0);
-       r600_pipe_state_add_reg(rstate,
-                               R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
-                               NULL, 0);
-       r600_pipe_state_add_reg(rstate,
-                               R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
-                               NULL, 0);
 
        r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
                                shader_control, NULL, 0);
@@ -1704,7 +1699,7 @@ void r600_init_state_functions(struct r600_context *rctx)
        rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
        rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
        rctx->context.set_sample_mask = r600_set_sample_mask;
-       rctx->context.set_scissor_state = r600_set_scissor_state;
+       rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
        rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
        rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
        rctx->context.set_index_buffer = r600_set_index_buffer;
@@ -2059,6 +2054,7 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
        }
 
        r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
+       r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
 
        if (rctx->chip_class >= R700) {
                r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);