r600g: check for PIPE_BIND_BLENDABLE in is_format_supported

[mesa.git] / src / gallium / drivers / r600 / r600_state.c

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 8053ff43ba882444f2e885e4201da7a0740f0df6..31d7bd045192318829fff3096eaf1b6d3b23ce87 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -157,6 +157,11 @@ static bool r600_is_zs_format_supported(enum pipe_format format)
        return r600_translate_dbformat(format) != ~0U;
 }
 
+static inline bool r600_is_blending_supported(enum pipe_format format)
+{
+       return !(util_format_is_pure_integer(format) || util_format_is_depth_or_stencil(format));
+}
+
 boolean r600_is_format_supported(struct pipe_screen *screen,
                                 enum pipe_format format,
                                 enum pipe_texture_target target,
@@ -235,6 +240,10 @@ boolean r600_is_format_supported(struct pipe_screen *screen,
        if (usage & PIPE_BIND_TRANSFER_WRITE)
                retval |= PIPE_BIND_TRANSFER_WRITE;
 
+       if ((usage & PIPE_BIND_BLENDABLE) &&
+           r600_is_blending_supported(format))
+               retval |= PIPE_BIND_BLENDABLE;
+
        return retval == usage;
 }
 
@@ -460,6 +469,10 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
                S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
                S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
                S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
+       if (rctx->b.chip_class == R700) {
+               rs->pa_cl_clip_cntl |=
+                       S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
+       }
        rs->multisample_enable = state->multisample;
 
        /* offset */
@@ -517,19 +530,25 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
                               S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
                               S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
        r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
-       r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL,
-                              S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
-                              S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
-                              S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
-                              S_028814_FACE(!state->front_ccw) |
-                              S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
-                              S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
-                              S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
-                              S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
-                                                 state->fill_back != PIPE_POLYGON_MODE_FILL) |
-                              S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
-                              S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
-       r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
+
+       rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
+                                S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
+                                S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
+                                S_028814_FACE(!state->front_ccw) |
+                                S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+                                S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+                                S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
+                                S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
+                                                                        state->fill_back != PIPE_POLYGON_MODE_FILL) |
+                                S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
+                                S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
+       if (rctx->b.chip_class == R700) {
+               r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
+       }
+       if (rctx->b.chip_class == R600) {
+               r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
+                                      S_028350_MULTIPASS(state->rasterizer_discard));
+       }
        return rs;
 }
 
@@ -1612,6 +1631,11 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom
                db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
        }
 
+       /* RV770 workaround for a hang with 8x MSAA. */
+       if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
+               db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
+       }
+
        r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
        radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
        radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
@@ -2389,8 +2413,11 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
 
        r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
 
+       if (rctx->b.chip_class == R700)
+               r600_store_context_reg(cb, R_028350_SX_MISC, 0);
        if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
                r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
+
        r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
        if (rctx->screen->b.has_streamout) {
                r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
@@ -2568,32 +2595,10 @@ void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *sha
                S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
                S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
                S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
-               S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport) |
-               S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
-}
-
-static unsigned r600_conv_prim_to_gs_out(unsigned mode)
-{
-       static const int prim_conv[] = {
-               V_028A6C_OUTPRIM_TYPE_POINTLIST,
-               V_028A6C_OUTPRIM_TYPE_LINESTRIP,
-               V_028A6C_OUTPRIM_TYPE_LINESTRIP,
-               V_028A6C_OUTPRIM_TYPE_LINESTRIP,
-               V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-               V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-               V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-               V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-               V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-               V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-               V_028A6C_OUTPRIM_TYPE_LINESTRIP,
-               V_028A6C_OUTPRIM_TYPE_LINESTRIP,
-               V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-               V_028A6C_OUTPRIM_TYPE_TRISTRIP,
-               V_028A6C_OUTPRIM_TYPE_TRISTRIP
-       };
-       assert(mode < Elements(prim_conv));
-
-       return prim_conv[mode];
+               S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
+               S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
+               S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
+               S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
 }
 
 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)