#include "util/u_inlines.h"
#include "util/u_format.h"
#include "util/u_memory.h"
+#include "util/u_pack_color.h"
#include "r600_screen.h"
#include "r600_context.h"
#include "r600_resource.h"
-#include "r600d.h"
-#include "r600_reg.h"
-#include "r600_state_inlines.h"
+
+static void clean_flush(struct r600_context *rctx, struct radeon_state *flush);
+static int setup_cb_flush(struct r600_context *rctx, struct radeon_state *flush);
+static int setup_db_flush(struct r600_context *rctx, struct radeon_state *flush);
+
+static struct r600_context_state *r600_new_context_state(unsigned type)
+{
+ struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
+ if (rstate == NULL)
+ return NULL;
+ rstate->type = type;
+ rstate->refcount = 1;
+ return rstate;
+}
static void *r600_create_blend_state(struct pipe_context *ctx,
const struct pipe_blend_state *state)
{
struct r600_context *rctx = r600_context(ctx);
+ struct r600_context_state *rstate;
- return r600_context_state(rctx, pipe_blend_type, state);
+ rstate = r600_new_context_state(pipe_blend_type);
+ rstate->state.blend = *state;
+ rctx->vtbl->blend(rctx, &rstate->rstate[0], &rstate->state.blend);
+
+ return rstate;
}
static void *r600_create_dsa_state(struct pipe_context *ctx,
- const struct pipe_depth_stencil_alpha_state *state)
+ const struct pipe_depth_stencil_alpha_state *state)
{
- struct r600_context *rctx = r600_context(ctx);
+ struct r600_context_state *rstate;
- return r600_context_state(rctx, pipe_dsa_type, state);
+ rstate = r600_new_context_state(pipe_dsa_type);
+ rstate->state.dsa = *state;
+ return rstate;
}
static void *r600_create_rs_state(struct pipe_context *ctx,
const struct pipe_rasterizer_state *state)
{
- struct r600_context *rctx = r600_context(ctx);
+ struct r600_context_state *rstate;
- return r600_context_state(rctx, pipe_rasterizer_type, state);
+ rstate = r600_new_context_state(pipe_rasterizer_type);
+ rstate->state.rasterizer = *state;
+ return rstate;
}
static void *r600_create_sampler_state(struct pipe_context *ctx,
const struct pipe_sampler_state *state)
{
struct r600_context *rctx = r600_context(ctx);
+ struct r600_context_state *rstate;
- return r600_context_state(rctx, pipe_sampler_type, state);
+ rstate = r600_new_context_state(pipe_sampler_type);
+ rstate->state.sampler = *state;
+ rctx->vtbl->sampler(rctx, &rstate->rstate[0], &rstate->state.sampler, 0);
+ rctx->vtbl->sampler_border(rctx, &rstate->rstate[1], &rstate->state.sampler, 0);
+ return rstate;
}
+static void r600_remove_sampler_view(struct r600_shader_sampler_states *sampler,
+ struct r600_context_state *rstate)
+{
+ int i, j;
+
+ for (i = 0; i < sampler->nview; i++) {
+ for (j = 0; j < rstate->nrstate; j++) {
+ if (sampler->view[i] == &rstate->rstate[j])
+ sampler->view[i] = NULL;
+ }
+ }
+}
static void r600_sampler_view_destroy(struct pipe_context *ctx,
struct pipe_sampler_view *state)
{
struct r600_context_state *rstate = (struct r600_context_state *)state;
+ struct r600_context *rctx = r600_context(ctx);
+ /* need to search list of vs/ps sampler views and remove it from any - uggh */
+ r600_remove_sampler_view(&rctx->ps_sampler, rstate);
+ r600_remove_sampler_view(&rctx->vs_sampler, rstate);
r600_context_state_decref(rstate);
}
struct pipe_resource *texture,
const struct pipe_sampler_view *state)
{
- struct r600_context *rctx = r600_context(ctx);
struct r600_context_state *rstate;
+ struct r600_context *rctx = r600_context(ctx);
- rstate = r600_context_state(rctx, pipe_sampler_type, state);
+ rstate = r600_new_context_state(pipe_sampler_view_type);
+ rstate->state.sampler_view = *state;
+ rstate->state.sampler_view.texture = NULL;
pipe_reference(NULL, &texture->reference);
rstate->state.sampler_view.texture = texture;
rstate->state.sampler_view.reference.count = 1;
rstate->state.sampler_view.context = ctx;
+ rctx->vtbl->resource(ctx, &rstate->rstate[0], &rstate->state.sampler_view, 0);
return &rstate->state.sampler_view;
}
+static void r600_set_sampler_view(struct pipe_context *ctx,
+ unsigned count,
+ struct pipe_sampler_view **views,
+ struct r600_shader_sampler_states *sampler,
+ unsigned shader_id)
+{
+ struct r600_context *rctx = r600_context(ctx);
+ struct r600_context_state *rstate;
+ unsigned i;
+
+ for (i = 0; i < sampler->nview; i++) {
+ radeon_draw_unbind(&rctx->draw, sampler->view[i]);
+ }
+
+ for (i = 0; i < count; i++) {
+ rstate = (struct r600_context_state *)views[i];
+ if (rstate) {
+ rstate->nrstate = 0;
+ }
+ }
+ for (i = 0; i < count; i++) {
+ rstate = (struct r600_context_state *)views[i];
+ if (rstate) {
+ if (rstate->nrstate >= R600_MAX_RSTATE)
+ continue;
+ if (rstate->nrstate) {
+ memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
+ }
+ radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, shader_id);
+ sampler->view[i] = &rstate->rstate[rstate->nrstate];
+ rstate->nrstate++;
+ }
+ }
+ sampler->nview = count;
+}
+
+static void r600_set_ps_sampler_view(struct pipe_context *ctx,
+ unsigned count,
+ struct pipe_sampler_view **views)
+{
+ struct r600_context *rctx = r600_context(ctx);
+ r600_set_sampler_view(ctx, count, views, &rctx->ps_sampler, R600_SHADER_PS);
+}
+
+static void r600_set_vs_sampler_view(struct pipe_context *ctx,
+ unsigned count,
+ struct pipe_sampler_view **views)
+{
+ struct r600_context *rctx = r600_context(ctx);
+ r600_set_sampler_view(ctx, count, views, &rctx->vs_sampler, R600_SHADER_VS);
+}
+
static void *r600_create_shader_state(struct pipe_context *ctx,
const struct pipe_shader_state *state)
{
struct r600_context *rctx = r600_context(ctx);
+ struct r600_context_state *rstate;
+ int r;
- return r600_context_state(rctx, pipe_shader_type, state);
+ rstate = r600_new_context_state(pipe_shader_type);
+ rstate->state.shader = *state;
+ r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
+ if (r) {
+ r600_context_state_decref(rstate);
+ return NULL;
+ }
+ return rstate;
}
static void *r600_create_vertex_elements(struct pipe_context *ctx,
return v;
}
-static void r600_bind_state(struct pipe_context *ctx, void *state)
+static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
{
- struct r600_context *rctx = r600_context(ctx);
- struct r600_context_state *rstate = (struct r600_context_state *)state;
+ struct r600_vertex_element *v = (struct r600_vertex_element*)state;
- if (state == NULL)
+ if (v == NULL)
return;
- switch (rstate->type) {
- case pipe_rasterizer_type:
- rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
- rctx->rasterizer = r600_context_state_incref(rstate);
- break;
- case pipe_poly_stipple_type:
- rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
- rctx->poly_stipple = r600_context_state_incref(rstate);
- break;
- case pipe_scissor_type:
- rctx->scissor = r600_context_state_decref(rctx->scissor);
- rctx->scissor = r600_context_state_incref(rstate);
- break;
- case pipe_clip_type:
- rctx->clip = r600_context_state_decref(rctx->clip);
- rctx->clip = r600_context_state_incref(rstate);
- break;
- case pipe_depth_type:
- rctx->depth = r600_context_state_decref(rctx->depth);
- rctx->depth = r600_context_state_incref(rstate);
- break;
- case pipe_stencil_type:
- rctx->stencil = r600_context_state_decref(rctx->stencil);
- rctx->stencil = r600_context_state_incref(rstate);
- break;
- case pipe_alpha_type:
- rctx->alpha = r600_context_state_decref(rctx->alpha);
- rctx->alpha = r600_context_state_incref(rstate);
- break;
- case pipe_dsa_type:
- rctx->dsa = r600_context_state_decref(rctx->dsa);
- rctx->dsa = r600_context_state_incref(rstate);
- break;
- case pipe_blend_type:
- rctx->blend = r600_context_state_decref(rctx->blend);
- rctx->blend = r600_context_state_incref(rstate);
- break;
- case pipe_framebuffer_type:
- rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
- rctx->framebuffer = r600_context_state_incref(rstate);
- break;
- case pipe_stencil_ref_type:
- rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
- rctx->stencil_ref = r600_context_state_incref(rstate);
- break;
- case pipe_viewport_type:
- rctx->viewport = r600_context_state_decref(rctx->viewport);
- rctx->viewport = r600_context_state_incref(rstate);
- break;
- case pipe_shader_type:
- case pipe_sampler_type:
- case pipe_sampler_view_type:
- default:
- R600_ERR("invalid type %d\n", rstate->type);
+ if (--v->refcount)
return;
+ free(v);
+}
+
+static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = r600_context(ctx);
+ struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+ r600_delete_vertex_element(ctx, rctx->vertex_elements);
+ rctx->vertex_elements = v;
+ if (v) {
+ v->refcount++;
}
}
-static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
+static void r600_bind_rasterizer_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = r600_context(ctx);
struct r600_context_state *rstate = (struct r600_context_state *)state;
- rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
- rctx->ps_shader = r600_context_state_incref(rstate);
+ if (state == NULL)
+ return;
+ rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
+ rctx->rasterizer = r600_context_state_incref(rstate);
}
-static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
+static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = r600_context(ctx);
struct r600_context_state *rstate = (struct r600_context_state *)state;
- rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
- rctx->vs_shader = r600_context_state_incref(rstate);
+ if (state == NULL)
+ return;
+ rctx->blend = r600_context_state_decref(rctx->blend);
+ rctx->blend = r600_context_state_incref(rstate);
+
}
-static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
+static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
{
- struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+ struct r600_context *rctx = r600_context(ctx);
+ struct r600_context_state *rstate = (struct r600_context_state *)state;
- if (v == NULL)
- return;
- if (--v->refcount)
+ if (state == NULL)
return;
- free(v);
+ rctx->dsa = r600_context_state_decref(rctx->dsa);
+ rctx->dsa = r600_context_state_incref(rstate);
}
-static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
+static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = r600_context(ctx);
- struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+ struct r600_context_state *rstate = (struct r600_context_state *)state;
- r600_delete_vertex_element(ctx, rctx->vertex_elements);
- rctx->vertex_elements = v;
- if (v) {
- v->refcount++;
- }
+ rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
+ rctx->ps_shader = r600_context_state_incref(rstate);
}
-static void r600_bind_ps_sampler(struct pipe_context *ctx,
- unsigned count, void **states)
+static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = r600_context(ctx);
+ struct r600_context_state *rstate = (struct r600_context_state *)state;
+
+ rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
+ rctx->vs_shader = r600_context_state_incref(rstate);
+}
+
+static void r600_bind_sampler_shader(struct pipe_context *ctx,
+ unsigned count, void **states,
+ struct r600_shader_sampler_states *sampler, unsigned shader_id)
{
struct r600_context *rctx = r600_context(ctx);
struct r600_context_state *rstate;
unsigned i;
- for (i = 0; i < rctx->ps_nsampler; i++) {
- rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
+ for (i = 0; i < sampler->nsampler; i++) {
+ radeon_draw_unbind(&rctx->draw, sampler->sampler[i]);
+ }
+ for (i = 0; i < sampler->nborder; i++) {
+ radeon_draw_unbind(&rctx->draw, sampler->border[i]);
+ }
+ for (i = 0; i < count; i++) {
+ rstate = (struct r600_context_state *)states[i];
+ if (rstate) {
+ rstate->nrstate = 0;
+ }
}
for (i = 0; i < count; i++) {
rstate = (struct r600_context_state *)states[i];
- rctx->ps_sampler[i] = r600_context_state_incref(rstate);
+ if (rstate) {
+ if (rstate->nrstate >= R600_MAX_RSTATE)
+ continue;
+ if (rstate->nrstate) {
+ memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
+ memcpy(&rstate->rstate[rstate->nrstate+1], &rstate->rstate[1], sizeof(struct radeon_state));
+ }
+ radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, shader_id);
+ radeon_state_convert(&rstate->rstate[rstate->nrstate + 1], R600_STATE_SAMPLER_BORDER, i, shader_id);
+ sampler->sampler[i] = &rstate->rstate[rstate->nrstate];
+ sampler->border[i] = &rstate->rstate[rstate->nrstate + 1];
+ rstate->nrstate += 2;
+ }
}
- rctx->ps_nsampler = count;
+ sampler->nsampler = count;
+ sampler->nborder = count;
}
-static void r600_bind_vs_sampler(struct pipe_context *ctx,
+static void r600_bind_ps_sampler(struct pipe_context *ctx,
unsigned count, void **states)
{
struct r600_context *rctx = r600_context(ctx);
- struct r600_context_state *rstate;
- unsigned i;
+ r600_bind_sampler_shader(ctx, count, states, &rctx->ps_sampler, R600_SHADER_PS);
+}
- for (i = 0; i < rctx->vs_nsampler; i++) {
- rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
- }
- for (i = 0; i < count; i++) {
- rstate = (struct r600_context_state *)states[i];
- rctx->vs_sampler[i] = r600_context_state_incref(rstate);
- }
- rctx->vs_nsampler = count;
+static void r600_bind_vs_sampler(struct pipe_context *ctx,
+ unsigned count, void **states)
+{
+ struct r600_context *rctx = r600_context(ctx);
+ r600_bind_sampler_shader(ctx, count, states, &rctx->vs_sampler, R600_SHADER_VS);
}
static void r600_delete_state(struct pipe_context *ctx, void *state)
static void r600_set_clip_state(struct pipe_context *ctx,
const struct pipe_clip_state *state)
{
-}
-
-static void r600_set_constant_buffer(struct pipe_context *ctx,
- uint shader, uint index,
- struct pipe_resource *buffer)
-{
- struct r600_screen *rscreen = r600_screen(ctx->screen);
struct r600_context *rctx = r600_context(ctx);
- unsigned nconstant = 0, i, type, id;
- struct radeon_state *rstate;
- struct pipe_transfer *transfer;
- u32 *ptr;
-
- switch (shader) {
- case PIPE_SHADER_VERTEX:
- id = R600_VS_CONSTANT;
- type = R600_VS_CONSTANT_TYPE;
- break;
- case PIPE_SHADER_FRAGMENT:
- id = R600_PS_CONSTANT;
- type = R600_PS_CONSTANT_TYPE;
- break;
- default:
- fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader);
- return;
- }
- if (buffer && buffer->width0 > 0) {
- nconstant = buffer->width0 / 16;
- ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
- if (ptr == NULL)
- return;
- for (i = 0; i < nconstant; i++) {
- rstate = radeon_state(rscreen->rw, type, id + i);
- if (rstate == NULL)
- return;
- rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
- rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
- rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
- rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
- if (radeon_state_pm4(rstate))
- return;
- if (radeon_draw_set_new(rctx->draw, rstate))
- return;
- }
- pipe_buffer_unmap(ctx, buffer, transfer);
- }
+ struct r600_context_state *rstate;
+
+ r600_context_state_decref(rctx->clip);
+
+ rstate = r600_new_context_state(pipe_clip_type);
+ rstate->state.clip = *state;
+ rctx->vtbl->ucp(rctx, &rstate->rstate[0], &rstate->state.clip);
+ rctx->clip = rstate;
}
-static void r600_set_ps_sampler_view(struct pipe_context *ctx,
- unsigned count,
- struct pipe_sampler_view **views)
+static void r600_set_framebuffer_state(struct pipe_context *ctx,
+ const struct pipe_framebuffer_state *state)
{
struct r600_context *rctx = r600_context(ctx);
struct r600_context_state *rstate;
- unsigned i;
+ int i;
- for (i = 0; i < rctx->ps_nsampler_view; i++) {
- rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
- }
- for (i = 0; i < count; i++) {
- rstate = (struct r600_context_state *)views[i];
- rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
+ if (rctx->framebuffer) {
+ for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++)
+ radeon_draw_unbind(&rctx->draw, &rctx->framebuffer->rstate[i+1]);
+ radeon_draw_unbind(&rctx->draw, &rctx->framebuffer->rstate[0]);
}
- rctx->ps_nsampler_view = count;
-}
+ clean_flush(rctx, &rctx->hw_states.cb_flush);
+ clean_flush(rctx, &rctx->hw_states.db_flush);
-static void r600_set_vs_sampler_view(struct pipe_context *ctx,
- unsigned count,
- struct pipe_sampler_view **views)
-{
- struct r600_context *rctx = r600_context(ctx);
- struct r600_context_state *rstate;
- unsigned i;
+ r600_context_state_decref(rctx->framebuffer);
- for (i = 0; i < rctx->vs_nsampler_view; i++) {
- rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
+ rstate = r600_new_context_state(pipe_framebuffer_type);
+ rstate->state.framebuffer = *state;
+ for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
+ pipe_reference(NULL, &state->cbufs[i]->reference);
}
- for (i = 0; i < count; i++) {
- rstate = (struct r600_context_state *)views[i];
- rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
+ pipe_reference(NULL, &state->zsbuf->reference);
+ rctx->framebuffer = rstate;
+ for (i = 0; i < state->nr_cbufs; i++) {
+ rctx->vtbl->cb(rctx, &rstate->rstate[i+1], state, i);
}
- rctx->vs_nsampler_view = count;
-}
-
-static void r600_set_framebuffer_state(struct pipe_context *ctx,
- const struct pipe_framebuffer_state *state)
-{
- struct r600_context *rctx = r600_context(ctx);
- struct r600_context_state *rstate;
+ if (state->zsbuf) {
+ rctx->vtbl->db(rctx, &rstate->rstate[0], state);
+ }
+ /* setup flush states */
+ setup_cb_flush(rctx, &rctx->hw_states.cb_flush);
+ setup_db_flush(rctx, &rctx->hw_states.db_flush);
- rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
- r600_bind_state(ctx, rstate);
+ return;
}
static void r600_set_polygon_stipple(struct pipe_context *ctx,
struct r600_context *rctx = r600_context(ctx);
struct r600_context_state *rstate;
- rstate = r600_context_state(rctx, pipe_scissor_type, state);
- r600_bind_state(ctx, rstate);
+ r600_context_state_decref(rctx->scissor);
+
+ rstate = r600_new_context_state(pipe_scissor_type);
+ rstate->state.scissor = *state;
+ rctx->scissor = rstate;
}
static void r600_set_stencil_ref(struct pipe_context *ctx,
struct r600_context *rctx = r600_context(ctx);
struct r600_context_state *rstate;
- rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
- r600_bind_state(ctx, rstate);
+ r600_context_state_decref(rctx->stencil_ref);
+
+ rstate = r600_new_context_state(pipe_stencil_ref_type);
+ rstate->state.stencil_ref = *state;
+ rctx->stencil_ref = rstate;
}
static void r600_set_vertex_buffers(struct pipe_context *ctx,
{
struct r600_context *rctx = r600_context(ctx);
unsigned i;
+ boolean any_user_buffers = FALSE;
for (i = 0; i < rctx->nvertex_buffer; i++) {
pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
for (i = 0; i < count; i++) {
rctx->vertex_buffer[i].buffer = NULL;
+ if (r600_buffer_is_user_buffer(buffers[i].buffer))
+ any_user_buffers = TRUE;
pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
}
+ rctx->any_user_vbs = any_user_buffers;
rctx->nvertex_buffer = count;
}
if (ib) {
pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
- }
- else {
+ } else {
pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
}
struct r600_context *rctx = r600_context(ctx);
struct r600_context_state *rstate;
- rstate = r600_context_state(rctx, pipe_viewport_type, state);
- r600_bind_state(ctx, rstate);
+ r600_context_state_decref(rctx->viewport);
+
+ rstate = r600_new_context_state(pipe_viewport_type);
+ rstate->state.viewport = *state;
+ rctx->vtbl->viewport(rctx, &rstate->rstate[0], &rstate->state.viewport);
+ rctx->viewport = rstate;
}
void r600_init_state_functions(struct r600_context *rctx)
rctx->context.create_sampler_view = r600_create_sampler_view;
rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
rctx->context.create_vs_state = r600_create_shader_state;
- rctx->context.bind_blend_state = r600_bind_state;
- rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
+ rctx->context.bind_blend_state = r600_bind_blend_state;
+ rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
rctx->context.bind_fs_state = r600_bind_ps_shader;
- rctx->context.bind_rasterizer_state = r600_bind_state;
+ rctx->context.bind_rasterizer_state = r600_bind_rasterizer_state;
rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
rctx->context.bind_vs_state = r600_bind_vs_shader;
rctx->context.delete_vs_state = r600_delete_state;
rctx->context.set_blend_color = r600_set_blend_color;
rctx->context.set_clip_state = r600_set_clip_state;
- rctx->context.set_constant_buffer = r600_set_constant_buffer;
+
+ if (radeon_get_family_class(rctx->rw) == EVERGREEN)
+ rctx->context.set_constant_buffer = eg_set_constant_buffer;
+ else if (rctx->screen->use_mem_constant)
+ rctx->context.set_constant_buffer = r600_set_constant_buffer_mem;
+ else
+ rctx->context.set_constant_buffer = r600_set_constant_buffer_file;
+
rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
case pipe_framebuffer_type:
for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
+ radeon_state_fini(&rstate->rstate[i+1]);
}
pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
break;
R600_ERR("invalid type %d\n", rstate->type);
return NULL;
}
- radeon_state_decref(rstate->rstate);
+ radeon_state_fini(&rstate->rstate[0]);
FREE(rstate);
return NULL;
}
-struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
+static void r600_bind_shader_sampler(struct r600_context *rctx, struct r600_shader_sampler_states *sampler)
{
- struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
- const union pipe_states *states = state;
- unsigned i;
- int r;
+ int i;
- if (rstate == NULL)
- return NULL;
- rstate->type = type;
- rstate->refcount = 1;
+ for (i = 0; i < sampler->nsampler; i++) {
+ if (sampler->sampler[i])
+ radeon_draw_bind(&rctx->draw, sampler->sampler[i]);
+ }
- switch (rstate->type) {
- case pipe_sampler_view_type:
- rstate->state.sampler_view = (*states).sampler_view;
- rstate->state.sampler_view.texture = NULL;
- break;
- case pipe_framebuffer_type:
- rstate->state.framebuffer = (*states).framebuffer;
- for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
- pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
- (*states).framebuffer.cbufs[i]);
- }
- pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
- (*states).framebuffer.zsbuf);
- break;
- case pipe_viewport_type:
- rstate->state.viewport = (*states).viewport;
- break;
- case pipe_depth_type:
- rstate->state.depth = (*states).depth;
- break;
- case pipe_rasterizer_type:
- rstate->state.rasterizer = (*states).rasterizer;
- break;
- case pipe_poly_stipple_type:
- rstate->state.poly_stipple = (*states).poly_stipple;
- break;
- case pipe_scissor_type:
- rstate->state.scissor = (*states).scissor;
- break;
- case pipe_clip_type:
- rstate->state.clip = (*states).clip;
- break;
- case pipe_stencil_type:
- rstate->state.stencil = (*states).stencil;
- break;
- case pipe_alpha_type:
- rstate->state.alpha = (*states).alpha;
- break;
- case pipe_dsa_type:
- rstate->state.dsa = (*states).dsa;
- break;
- case pipe_blend_type:
- rstate->state.blend = (*states).blend;
- break;
- case pipe_stencil_ref_type:
- rstate->state.stencil_ref = (*states).stencil_ref;
- break;
- case pipe_shader_type:
- rstate->state.shader = (*states).shader;
- r = r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
- if (r) {
- r600_context_state_decref(rstate);
- return NULL;
- }
- break;
- case pipe_sampler_type:
- rstate->state.sampler = (*states).sampler;
- break;
- default:
- R600_ERR("invalid type %d\n", rstate->type);
- FREE(rstate);
- return NULL;
+ for (i = 0; i < sampler->nborder; i++) {
+ if (sampler->border[i])
+ radeon_draw_bind(&rctx->draw, sampler->border[i]);
+ }
+
+ for (i = 0; i < sampler->nview; i++) {
+ if (sampler->view[i])
+ radeon_draw_bind(&rctx->draw, sampler->view[i]);
}
- return rstate;
}
-static struct radeon_state *r600_blend(struct r600_context *rctx)
+static void clean_flush(struct r600_context *rctx, struct radeon_state *flush)
{
struct r600_screen *rscreen = rctx->screen;
- struct radeon_state *rstate;
- const struct pipe_blend_state *state = &rctx->blend->state.blend;
int i;
- rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
- if (rstate == NULL)
- return NULL;
- rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
- rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
- rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
- rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
- rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
- rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
- rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
- rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
- rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
- rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
- rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
- rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
- rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
-
- for (i = 0; i < 8; i++) {
-
- unsigned eqRGB = state->rt[i].rgb_func;
- unsigned srcRGB = state->rt[i].rgb_src_factor;
- unsigned dstRGB = state->rt[i].rgb_dst_factor;
-
- unsigned eqA = state->rt[i].alpha_func;
- unsigned srcA = state->rt[i].alpha_src_factor;
- unsigned dstA = state->rt[i].alpha_dst_factor;
- uint32_t bc = 0;
-
- if (!state->rt[i].blend_enable)
- continue;
-
- bc |= r600_translate_blend_function(eqRGB) << CB_BLEND_COLOR_COMB_FCN_SHIFT;
- bc |= r600_translate_blend_factor(srcRGB) << CB_BLEND_COLOR_SRCBLEND_SHIFT;
- bc |= r600_translate_blend_factor(dstRGB) << CB_BLEND_COLOR_DESTBLEND_SHIFT;
-
- if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
- bc |= CB_BLEND_SEPARATE_ALPHA_BLEND;
- bc |= r600_translate_blend_function(eqA) << CB_BLEND_ALPHA_COMB_FCN_SHIFT;
- bc |= r600_translate_blend_factor(srcA) << CB_BLEND_ALPHA_SRCBLEND_SHIFT;
- bc |= r600_translate_blend_factor(dstA) << CB_BLEND_ALPHA_DESTBLEND_SHIFT;
- }
-
- rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
- if (i == 0)
- rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
+ for (i = 0 ; i < flush->nbo; i++) {
+ radeon_ws_bo_reference(rscreen->rw, &flush->bo[i], NULL);
}
-
- if (radeon_state_pm4(rstate)) {
- radeon_state_decref(rstate);
- return NULL;
- }
- return rstate;
+ flush->nbo = 0;
+ radeon_state_fini(flush);
}
-static struct radeon_state *r600_cb0(struct r600_context *rctx)
+static int setup_cb_flush(struct r600_context *rctx, struct radeon_state *flush)
{
struct r600_screen *rscreen = rctx->screen;
struct r600_resource_texture *rtex;
struct r600_resource *rbuffer;
- struct radeon_state *rstate;
- const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
- unsigned level = state->cbufs[0]->level;
- unsigned pitch, slice;
+ struct pipe_surface *surf;
+ int i;
- rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
- if (rstate == NULL)
- return NULL;
- rtex = (struct r600_resource_texture*)state->cbufs[0]->texture;
- rbuffer = &rtex->resource;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
- rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
- rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
- rstate->nbo = 3;
- pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
- slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[0]->height / 64 - 1;
- rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
- rstate->states[R600_CB0__CB_COLOR0_INFO] = 0x08110068;
- rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
- S_028060_SLICE_TILE_MAX(slice);
- rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
- rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
- rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
- rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
- if (radeon_state_pm4(rstate)) {
- radeon_state_decref(rstate);
- return NULL;
- }
- return rstate;
-}
+ radeon_state_init(flush, rscreen->rw, R600_STATE_CB_FLUSH, 0, 0);
-static int r600_db_format(unsigned pformat, unsigned *format)
-{
- switch (pformat) {
- case PIPE_FORMAT_Z24X8_UNORM:
- *format = V_028010_DEPTH_X8_24;
- return 0;
- case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
- *format = V_028010_DEPTH_8_24;
- return 0;
- default:
- *format = V_028010_DEPTH_INVALID;
- R600_ERR("unsupported %d\n", pformat);
- return -EINVAL;
+ for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
+ surf = rctx->framebuffer->state.framebuffer.cbufs[i];
+
+ rtex = (struct r600_resource_texture*)surf->texture;
+ rbuffer = &rtex->resource;
+ /* just need to the bo to the flush list */
+ radeon_ws_bo_reference(rscreen->rw, &flush->bo[i], rbuffer->bo);
+ flush->placement[i] = RADEON_GEM_DOMAIN_VRAM;
}
+ flush->nbo = rctx->framebuffer->state.framebuffer.nr_cbufs;
+ return radeon_state_pm4(flush);
}
-static struct radeon_state *r600_db(struct r600_context *rctx)
+static int setup_db_flush(struct r600_context *rctx, struct radeon_state *flush)
{
struct r600_screen *rscreen = rctx->screen;
struct r600_resource_texture *rtex;
struct r600_resource *rbuffer;
- struct radeon_state *rstate;
- const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
- unsigned level = state->cbufs[0]->level;
- unsigned pitch, slice, format;
+ struct pipe_surface *surf;
- if (state->zsbuf == NULL)
- return NULL;
+ surf = rctx->framebuffer->state.framebuffer.zsbuf;
- rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
- if (rstate == NULL)
- return NULL;
-
- rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+ if (!surf)
+ return 0;
+
+ radeon_state_init(flush, rscreen->rw, R600_STATE_DB_FLUSH, 0, 0);
+ rtex = (struct r600_resource_texture*)surf->texture;
rbuffer = &rtex->resource;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->nbo = 1;
- rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
- level = state->zsbuf->level;
- pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
- slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
- if (r600_db_format(state->zsbuf->texture->format, &format)) {
- radeon_state_decref(rstate);
- return NULL;
- }
- rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
- rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
- S_028010_FORMAT(format);
- rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
- rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
- rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
- S_028000_SLICE_TILE_MAX(slice);
- if (radeon_state_pm4(rstate)) {
- radeon_state_decref(rstate);
- return NULL;
- }
- return rstate;
-}
-
-static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
-{
- const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
- struct r600_screen *rscreen = rctx->screen;
- struct radeon_state *rstate;
+ /* just need to the bo to the flush list */
+ radeon_ws_bo_reference(rscreen->rw, &flush->bo[0], rbuffer->bo);
+ flush->placement[0] = RADEON_GEM_DOMAIN_VRAM;
- rctx->flat_shade = state->flatshade;
- rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
- if (rstate == NULL)
- return NULL;
- rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
- rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
- rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 |
- S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
- S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
- S_028814_FACE(!state->front_ccw);
- rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000;
- rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
- rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008;
- rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x00000000;
- rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
- rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
- rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
- rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
- rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
- rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
- rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
- rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
- rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = 0x00000000;
- rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
- rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = 0x00000000;
- rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = 0x00000000;
- rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = 0x00000000;
- rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = 0x00000000;
- if (radeon_state_pm4(rstate)) {
- radeon_state_decref(rstate);
- return NULL;
- }
- return rstate;
+ flush->nbo = 1;
+ return radeon_state_pm4(flush);
}
-static struct radeon_state *r600_scissor(struct r600_context *rctx)
+int r600_context_hw_states(struct pipe_context *ctx)
{
- const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
- struct r600_screen *rscreen = rctx->screen;
- struct radeon_state *rstate;
- u32 tl, br;
-
- tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
- br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
- rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
- if (rstate == NULL)
- return NULL;
- rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
- rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
- rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
- rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
- rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
- rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
- rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
- rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
- rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
- rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
- if (radeon_state_pm4(rstate)) {
- radeon_state_decref(rstate);
- return NULL;
- }
- return rstate;
-}
-
-static struct radeon_state *r600_viewport(struct r600_context *rctx)
-{
- const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
- struct r600_screen *rscreen = rctx->screen;
- struct radeon_state *rstate;
-
- rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
- if (rstate == NULL)
- return NULL;
- rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
- rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
- rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
- rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
- rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
- rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
- rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
- rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
- rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
- if (radeon_state_pm4(rstate)) {
- radeon_state_decref(rstate);
- return NULL;
- }
- return rstate;
-}
-
-static struct radeon_state *r600_dsa(struct r600_context *rctx)
-{
- const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
- struct r600_screen *rscreen = rctx->screen;
- struct radeon_state *rstate;
- unsigned db_depth_control, alpha_test_control, alpha_ref;
+ struct r600_context *rctx = r600_context(ctx);
+ unsigned i;
- rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
- if (rstate == NULL)
- return NULL;
-
- db_depth_control = 0x00700700 | S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func);
- alpha_test_control = 0;
- alpha_ref = 0;
- if (state->alpha.enabled) {
- alpha_test_control = (state->alpha.func) << 0;
- alpha_test_control |= SX_ALPHA_TEST_ENABLE;
- alpha_ref = fui(state->alpha.ref_value);
- }
-
- rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
- rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
- rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
- rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00;
- rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00;
- rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
- rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
- rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
- rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
- rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
- rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
- rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
- rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
- rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
- rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
- rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
- if (radeon_state_pm4(rstate)) {
- radeon_state_decref(rstate);
- return NULL;
- }
- return rstate;
-}
-
-static inline unsigned r600_tex_wrap(unsigned wrap)
-{
- switch (wrap) {
- default:
- case PIPE_TEX_WRAP_REPEAT:
- return V_03C000_SQ_TEX_WRAP;
- case PIPE_TEX_WRAP_CLAMP:
- return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
- case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
- return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
- case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
- return V_03C000_SQ_TEX_CLAMP_BORDER;
- case PIPE_TEX_WRAP_MIRROR_REPEAT:
- return V_03C000_SQ_TEX_MIRROR;
- case PIPE_TEX_WRAP_MIRROR_CLAMP:
- return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
- case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
- return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
- case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
- return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
- }
-}
-
-static inline unsigned r600_tex_filter(unsigned filter)
-{
- switch (filter) {
- default:
- case PIPE_TEX_FILTER_NEAREST:
- return V_03C000_SQ_TEX_XY_FILTER_POINT;
- case PIPE_TEX_FILTER_LINEAR:
- return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
- }
-}
-
-static inline unsigned r600_tex_mipfilter(unsigned filter)
-{
- switch (filter) {
- case PIPE_TEX_MIPFILTER_NEAREST:
- return V_03C000_SQ_TEX_Z_FILTER_POINT;
- case PIPE_TEX_MIPFILTER_LINEAR:
- return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
- default:
- case PIPE_TEX_MIPFILTER_NONE:
- return V_03C000_SQ_TEX_Z_FILTER_NONE;
- }
-}
-
-static inline unsigned r600_tex_compare(unsigned compare)
-{
- switch (compare) {
- default:
- case PIPE_FUNC_NEVER:
- return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
- case PIPE_FUNC_LESS:
- return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
- case PIPE_FUNC_EQUAL:
- return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
- case PIPE_FUNC_LEQUAL:
- return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
- case PIPE_FUNC_GREATER:
- return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
- case PIPE_FUNC_NOTEQUAL:
- return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
- case PIPE_FUNC_GEQUAL:
- return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
- case PIPE_FUNC_ALWAYS:
- return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
- }
-}
-
-static INLINE u32 S_FIXED(float value, u32 frac_bits)
-{
- return value * (1 << frac_bits);
-}
-
-static struct radeon_state *r600_sampler(struct r600_context *rctx,
- const struct pipe_sampler_state *state,
- unsigned id)
-{
- struct r600_screen *rscreen = rctx->screen;
- struct radeon_state *rstate;
-
- rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
- if (rstate == NULL)
- return NULL;
- rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
- S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
- S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
- S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
- S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
- S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
- S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
- S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
- /* FIXME LOD it depends on texture base level ... */
- rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
- S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
- S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
- S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
- rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
- if (radeon_state_pm4(rstate)) {
- radeon_state_decref(rstate);
- return NULL;
- }
- return rstate;
-}
+ /* build new states */
+ rctx->vtbl->rasterizer(rctx, &rctx->hw_states.rasterizer);
+ rctx->vtbl->scissor(rctx, &rctx->hw_states.scissor);
+ rctx->vtbl->dsa(rctx, &rctx->hw_states.dsa);
+ rctx->vtbl->cb_cntl(rctx, &rctx->hw_states.cb_cntl);
+
+ /* bind states */
+ radeon_draw_bind(&rctx->draw, &rctx->config);
-static inline unsigned r600_tex_swizzle(unsigned swizzle)
-{
- switch (swizzle) {
- case PIPE_SWIZZLE_RED:
- return V_038010_SQ_SEL_X;
- case PIPE_SWIZZLE_GREEN:
- return V_038010_SQ_SEL_Y;
- case PIPE_SWIZZLE_BLUE:
- return V_038010_SQ_SEL_Z;
- case PIPE_SWIZZLE_ALPHA:
- return V_038010_SQ_SEL_W;
- case PIPE_SWIZZLE_ZERO:
- return V_038010_SQ_SEL_0;
- default:
- case PIPE_SWIZZLE_ONE:
- return V_038010_SQ_SEL_1;
- }
-}
+ radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
+ radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
+ radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
+ radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
-static inline unsigned r600_format_type(unsigned format_type)
-{
- switch (format_type) {
- default:
- case UTIL_FORMAT_TYPE_UNSIGNED:
- return V_038010_SQ_FORMAT_COMP_UNSIGNED;
- case UTIL_FORMAT_TYPE_SIGNED:
- return V_038010_SQ_FORMAT_COMP_SIGNED;
- case UTIL_FORMAT_TYPE_FIXED:
- return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
- }
-}
+ radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush);
+ radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush);
-static inline unsigned r600_tex_dim(unsigned dim)
-{
- switch (dim) {
- default:
- case PIPE_TEXTURE_1D:
- return V_038000_SQ_TEX_DIM_1D;
- case PIPE_TEXTURE_2D:
- return V_038000_SQ_TEX_DIM_2D;
- case PIPE_TEXTURE_3D:
- return V_038000_SQ_TEX_DIM_3D;
- case PIPE_TEXTURE_CUBE:
- return V_038000_SQ_TEX_DIM_CUBEMAP;
+ if (rctx->viewport) {
+ radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]);
}
-}
-
-static struct radeon_state *r600_resource(struct r600_context *rctx,
- const struct pipe_sampler_view *view,
- unsigned id)
-{
- struct r600_screen *rscreen = rctx->screen;
- const struct util_format_description *desc;
- struct r600_resource_texture *tmp;
- struct r600_resource *rbuffer;
- struct radeon_state *rstate;
- unsigned format;
-
- if (r600_conv_pipe_format(view->texture->format, &format))
- return NULL;
- desc = util_format_description(view->texture->format);
- assert(desc == NULL);
- rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
- if (rstate == NULL) {
- return NULL;
+ if (rctx->blend) {
+ radeon_draw_bind(&rctx->draw, &rctx->blend->rstate[0]);
}
- tmp = (struct r600_resource_texture*)view->texture;
- rbuffer = &tmp->resource;
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->nbo = 2;
- rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
- rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
- rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
- rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
-
- /* FIXME properly handle first level != 0 */
- rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
- S_038000_DIM(r600_tex_dim(view->texture->target)) |
- S_038000_PITCH(((tmp->pitch[0] / tmp->bpt) / 8) - 1) |
- S_038000_TEX_WIDTH(view->texture->width0 - 1);
- rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
- S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
- S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
- S_038004_DATA_FORMAT(format);
- rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
- rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
- rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
- S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
- S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
- S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
- S_038010_FORMAT_COMP_W(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
- S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
- S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
- S_038010_REQUEST_SIZE(1) |
- S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_b)) |
- S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) |
- S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_r)) |
- S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
- S_038010_BASE_LEVEL(view->first_level);
- rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
- S_038014_LAST_LEVEL(view->last_level) |
- S_038014_BASE_ARRAY(0) |
- S_038014_LAST_ARRAY(0);
- rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
- S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
- if (radeon_state_pm4(rstate)) {
- radeon_state_decref(rstate);
- return NULL;
+ if (rctx->clip) {
+ radeon_draw_bind(&rctx->draw, &rctx->clip->rstate[0]);
}
- return rstate;
-}
-
-static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
-{
- struct r600_screen *rscreen = rctx->screen;
- struct radeon_state *rstate;
- const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
- uint32_t color_control, target_mask;
- int i;
-
- target_mask = 0;
- color_control = 0;
-
- if (pbs->logicop_enable) {
- color_control |= (pbs->logicop_func) << 16;
- } else
- color_control |= (0xcc << 16);
-
- target_mask |= (pbs->rt[0].colormask);
- for (i = 0; i < 8; i++) {
- if (pbs->rt[i].blend_enable) {
- color_control |= (1 << (8 + i));
- target_mask |= (pbs->rt[0].colormask << (4 * i));
- } else if (i == 0)
- target_mask |= 0xf;
- }
- rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
- rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
- rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
- rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
- rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
- rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
- rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
- rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
- rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
- rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
- rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
- rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
- if (radeon_state_pm4(rstate)) {
- radeon_state_decref(rstate);
- return NULL;
- }
- return rstate;
-}
-
-int r600_context_hw_states(struct r600_context *rctx)
-{
- unsigned i;
- int r;
-
- /* free previous TODO determine what need to be updated, what
- * doesn't
- */
- //radeon_state_decref(rctx->hw_states.config);
- radeon_state_decref(rctx->hw_states.cb_cntl);
- radeon_state_decref(rctx->hw_states.db);
- radeon_state_decref(rctx->hw_states.rasterizer);
- radeon_state_decref(rctx->hw_states.scissor);
- radeon_state_decref(rctx->hw_states.dsa);
- radeon_state_decref(rctx->hw_states.blend);
- radeon_state_decref(rctx->hw_states.viewport);
- radeon_state_decref(rctx->hw_states.cb0);
- for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
- radeon_state_decref(rctx->hw_states.ps_resource[i]);
- rctx->hw_states.ps_resource[i] = NULL;
+ for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
+ radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[i+1]);
}
- rctx->hw_states.ps_nresource = 0;
- for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
- radeon_state_decref(rctx->hw_states.ps_sampler[i]);
- rctx->hw_states.ps_sampler[i] = NULL;
+ if (rctx->framebuffer->state.framebuffer.zsbuf) {
+ radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[0]);
}
- rctx->hw_states.ps_nsampler = 0;
- /* build new states */
- rctx->hw_states.rasterizer = r600_rasterizer(rctx);
- rctx->hw_states.scissor = r600_scissor(rctx);
- rctx->hw_states.dsa = r600_dsa(rctx);
- rctx->hw_states.blend = r600_blend(rctx);
- rctx->hw_states.viewport = r600_viewport(rctx);
- rctx->hw_states.cb0 = r600_cb0(rctx);
- rctx->hw_states.db = r600_db(rctx);
- rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
-
- for (i = 0; i < rctx->ps_nsampler; i++) {
- if (rctx->ps_sampler[i]) {
- rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
- &rctx->ps_sampler[i]->state.sampler,
- R600_PS_SAMPLER + i);
- }
- }
- rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
- for (i = 0; i < rctx->ps_nsampler_view; i++) {
- if (rctx->ps_sampler_view[i]) {
- rctx->hw_states.ps_resource[i] = r600_resource(rctx,
- &rctx->ps_sampler_view[i]->state.sampler_view,
- R600_PS_RESOURCE + i);
- }
- }
- rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
+ r600_bind_shader_sampler(rctx, &rctx->vs_sampler);
+ r600_bind_shader_sampler(rctx, &rctx->ps_sampler);
- /* bind states */
- r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
- if (r)
- return r;
- r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
- if (r)
- return r;
- r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
- if (r)
- return r;
- r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
- if (r)
- return r;
- r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
- if (r)
- return r;
- r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
- if (r)
- return r;
- r = radeon_draw_set(rctx->draw, rctx->hw_states.cb0);
- if (r)
- return r;
- r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
- if (r)
- return r;
- r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
- if (r)
- return r;
- for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
- if (rctx->hw_states.ps_resource[i]) {
- r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
- if (r)
- return r;
- }
- }
- for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
- if (rctx->hw_states.ps_sampler[i]) {
- r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
- if (r)
- return r;
- }
- }
return 0;
}
projects / mesa.git / blobdiff