gallium: change pipe_sampler_view::first_element/last_element -> offset/size

[mesa.git] / src / gallium / drivers / r600 / r600_state.c

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 89a9f25b4258aecee149d3bc422b5296e41107cf..62b1c2c282a8c2242522183fa5e9a67a974a3eb8 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -631,8 +631,8 @@ texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
        struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
        int stride = util_format_get_blocksize(view->base.format);
        unsigned format, num_format, format_comp, endian;
-       uint64_t offset = view->base.u.buf.first_element * stride;
-       unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
+       uint64_t offset = view->base.u.buf.offset;
+       unsigned size = view->base.u.buf.size;
 
        r600_vertex_data_type(view->base.format,
                              &format, &num_format, &format_comp,
@@ -695,7 +695,7 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
        swizzle[3] = state->swizzle_a;
 
        if (R600_BIG_ENDIAN)
-               do_endian_swap = !(tmp->is_depth && !tmp->is_flushing_texture);
+               do_endian_swap = !tmp->db_compatible;
 
        format = r600_translate_texformat(ctx->screen, state->format,
                                          swizzle,
@@ -706,7 +706,13 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
                return NULL;
        }
 
-       if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
+       if (state->format == PIPE_FORMAT_X24S8_UINT ||
+           state->format == PIPE_FORMAT_S8X24_UINT ||
+           state->format == PIPE_FORMAT_X32_S8X24_UINT ||
+           state->format == PIPE_FORMAT_S8_UINT)
+               view->is_stencil_sampler = true;
+
+       if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
                if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
                        FREE(view);
                        return NULL;
@@ -744,12 +750,6 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
                break;
        }
 
-       if (state->format == PIPE_FORMAT_X24S8_UINT ||
-           state->format == PIPE_FORMAT_S8X24_UINT ||
-           state->format == PIPE_FORMAT_X32_S8X24_UINT ||
-           state->format == PIPE_FORMAT_S8_UINT)
-               view->is_stencil_sampler = true;
-
        view->tex_resource = &tmp->resource;
        view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
                                       S_038000_TILE_MODE(array_mode) |
@@ -842,7 +842,7 @@ static void r600_init_color_surface(struct r600_context *rctx,
        int i;
        bool blend_bypass = 0, blend_clamp = 1, do_endian_swap = FALSE;
 
-       if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
+       if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) {
                r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
                rtex = rtex->flushed_depth_texture;
                assert(rtex);
@@ -895,7 +895,7 @@ static void r600_init_color_surface(struct r600_context *rctx,
        }
 
        if (R600_BIG_ENDIAN)
-               do_endian_swap = !(rtex->is_depth && !rtex->is_flushing_texture);
+               do_endian_swap = !rtex->db_compatible;
 
        format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
                                                      do_endian_swap);
@@ -967,10 +967,8 @@ static void r600_init_color_surface(struct r600_context *rctx,
        surf->cb_color_cmask = surf->cb_color_base;
        surf->cb_color_mask = 0;
 
-       pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
-                               &rtex->resource.b.b);
-       pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
-                               &rtex->resource.b.b);
+       r600_resource_reference(&surf->cb_buffer_cmask, &rtex->resource);
+       r600_resource_reference(&surf->cb_buffer_fmask, &rtex->resource);
 
        if (rtex->cmask.size) {
                surf->cb_color_cmask = rtex->cmask.offset >> 8;
@@ -1003,7 +1001,7 @@ static void r600_init_color_surface(struct r600_context *rctx,
                        struct pipe_transfer *transfer;
                        void *ptr;
 
-                       pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
+                       r600_resource_reference(&rctx->dummy_cmask, NULL);
                        rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
 
                        /* Set the contents to 0xCC. */
@@ -1011,19 +1009,17 @@ static void r600_init_color_surface(struct r600_context *rctx,
                        memset(ptr, 0xCC, cmask.size);
                        pipe_buffer_unmap(&rctx->b.b, transfer);
                }
-               pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
-                                       &rctx->dummy_cmask->b.b);
+               r600_resource_reference(&surf->cb_buffer_cmask, rctx->dummy_cmask);
 
                /* FMASK. */
                if (!rctx->dummy_fmask ||
                    rctx->dummy_fmask->b.b.width0 < fmask.size ||
                    rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
-                       pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
+                       r600_resource_reference(&rctx->dummy_fmask, NULL);
                        rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
 
                }
-               pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
-                                       &rctx->dummy_fmask->b.b);
+               r600_resource_reference(&surf->cb_buffer_fmask, rctx->dummy_fmask);
 
                /* Init the registers. */
                color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
@@ -1967,7 +1963,7 @@ static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
                radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
                                                      RADEON_USAGE_READWRITE,
-                                                     RADEON_PRIO_RINGS_STREAMOUT));
+                                                     RADEON_PRIO_SHADER_RINGS));
                radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
                                state->esgs_ring.buffer_size >> 8);
 
@@ -1976,7 +1972,7 @@ static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
                radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
                radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
                                                      RADEON_USAGE_READWRITE,
-                                                     RADEON_PRIO_RINGS_STREAMOUT));
+                                                     RADEON_PRIO_SHADER_RINGS));
                radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
                                state->gsvs_ring.buffer_size >> 8);
        } else {