struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
int stride = util_format_get_blocksize(view->base.format);
unsigned format, num_format, format_comp, endian;
- uint64_t offset = view->base.u.buf.first_element * stride;
- unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride;
+ uint64_t offset = view->base.u.buf.offset;
+ unsigned size = view->base.u.buf.size;
r600_vertex_data_type(view->base.format,
&format, &num_format, &format_comp,
swizzle[3] = state->swizzle_a;
if (R600_BIG_ENDIAN)
- do_endian_swap = !(tmp->is_depth && !tmp->is_flushing_texture);
+ do_endian_swap = !tmp->db_compatible;
format = r600_translate_texformat(ctx->screen, state->format,
swizzle,
return NULL;
}
- if (tmp->is_depth && !tmp->is_flushing_texture && !r600_can_read_depth(tmp)) {
+ if (state->format == PIPE_FORMAT_X24S8_UINT ||
+ state->format == PIPE_FORMAT_S8X24_UINT ||
+ state->format == PIPE_FORMAT_X32_S8X24_UINT ||
+ state->format == PIPE_FORMAT_S8_UINT)
+ view->is_stencil_sampler = true;
+
+ if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
FREE(view);
return NULL;
break;
}
- if (state->format == PIPE_FORMAT_X24S8_UINT ||
- state->format == PIPE_FORMAT_S8X24_UINT ||
- state->format == PIPE_FORMAT_X32_S8X24_UINT ||
- state->format == PIPE_FORMAT_S8_UINT)
- view->is_stencil_sampler = true;
-
view->tex_resource = &tmp->resource;
view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
S_038000_TILE_MODE(array_mode) |
int i;
bool blend_bypass = 0, blend_clamp = 1, do_endian_swap = FALSE;
- if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
+ if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) {
r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
rtex = rtex->flushed_depth_texture;
assert(rtex);
}
if (R600_BIG_ENDIAN)
- do_endian_swap = !(rtex->is_depth && !rtex->is_flushing_texture);
+ do_endian_swap = !rtex->db_compatible;
format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
do_endian_swap);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
- RADEON_PRIO_RINGS_STREAMOUT));
+ RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
state->esgs_ring.buffer_size >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
- RADEON_PRIO_RINGS_STREAMOUT));
+ RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
state->gsvs_ring.buffer_size >> 8);
} else {