* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
+#include "r600_formats.h"
+#include "r600d.h"
-#include <stdio.h>
-#include <errno.h>
-#include "pipe/p_defines.h"
-#include "pipe/p_state.h"
-#include "pipe/p_context.h"
-#include "tgsi/tgsi_scan.h"
-#include "tgsi/tgsi_parse.h"
-#include "tgsi/tgsi_util.h"
-#include "util/u_double_list.h"
+#include "pipe/p_shader_tokens.h"
#include "util/u_pack_color.h"
#include "util/u_memory.h"
-#include "util/u_inlines.h"
#include "util/u_framebuffer.h"
-#include "util/u_transfer.h"
-#include "pipebuffer/pb_buffer.h"
-#include "r600.h"
-#include "r600d.h"
-#include "r600_resource.h"
-#include "r600_shader.h"
-#include "r600_pipe.h"
-#include "r600_formats.h"
+#include "util/u_dual_blend.h"
static uint32_t r600_translate_blend_function(int blend_func)
{
case PIPE_FORMAT_R16G16_FLOAT:
case PIPE_FORMAT_R16G16_UINT:
case PIPE_FORMAT_R16G16_SINT:
+ case PIPE_FORMAT_R16G16B16_FLOAT:
+ case PIPE_FORMAT_R32G32B32_FLOAT:
case PIPE_FORMAT_R32_UINT:
case PIPE_FORMAT_R32_SINT:
case PIPE_FORMAT_R32_FLOAT:
float offset_units = rctx->rasterizer->offset_units;
unsigned offset_db_fmt_cntl = 0, depth;
- switch (rctx->framebuffer.zsbuf->texture->format) {
+ switch (rctx->framebuffer.zsbuf->format) {
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
depth = -24;
offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
r600_pipe_state_add_reg(&state,
R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
- fui(rctx->rasterizer->offset_scale), NULL, 0);
+ fui(rctx->rasterizer->offset_scale));
r600_pipe_state_add_reg(&state,
R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
- fui(offset_units), NULL, 0);
+ fui(offset_units));
r600_pipe_state_add_reg(&state,
R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
- fui(rctx->rasterizer->offset_scale), NULL, 0);
+ fui(rctx->rasterizer->offset_scale));
r600_pipe_state_add_reg(&state,
R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
- fui(offset_units), NULL, 0);
+ fui(offset_units));
r600_pipe_state_add_reg(&state,
R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
- offset_db_fmt_cntl, NULL, 0);
+ offset_db_fmt_cntl);
r600_context_pipe_state_set(rctx, &state);
}
}
target_mask |= (state->rt[0].colormask << (4 * i));
}
}
+
+ if (target_mask)
+ color_control |= S_028808_SPECIAL_OP(V_028808_NORMAL);
+ else
+ color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
+
blend->cb_target_mask = target_mask;
blend->cb_color_control = color_control;
-
+ /* only MRT0 has dual src blend */
+ blend->dual_src_blend = util_blend_state_is_dual(state, 0);
for (int i = 0; i < 8; i++) {
/* state->rt entries > 0 only written if independent blending */
const int j = state->independent_blend_enable ? i : 0;
/* R600 does not support per-MRT blends */
if (rctx->family > CHIP_R600)
- r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
if (i == 0)
- r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
}
return rstate;
}
alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
alpha_ref = fui(state->alpha.ref_value);
}
+ dsa->sx_alpha_test_control = alpha_test_control & 0xff;
dsa->alpha_ref = alpha_ref;
- r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
return rstate;
}
tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
}
}
- r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
/* point size 12.4 fixed point */
- /* For rasterizer discard, disable point rendering by forcing the point size to be 0. */
- tmp = state->rasterizer_discard ? 0 : r600_pack_float_12p4(state->point_size/2);
- r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
-
- if (state->rasterizer_discard) {
- /* For rasterizer discard, disable point rendering by forcing the point size to be 0. */
- psize_min = 0;
- psize_max = 0;
- } else if (state->point_size_per_vertex) {
+ tmp = r600_pack_float_12p4(state->point_size/2);
+ r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
+
+ if (state->point_size_per_vertex) {
psize_min = util_get_min_point_size(state);
psize_max = 8192;
} else {
/* Divide by two, because 0.5 = 1 pixel. */
r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
- S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
- NULL, 0);
+ S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
- /* For rasterizer discard, disable line rendering by forcing the line width to be 0. */
- tmp = state->rasterizer_discard ? 0 : r600_pack_float_12p4(state->line_width/2);
- r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
+ tmp = r600_pack_float_12p4(state->line_width/2);
+ r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
if (rctx->chip_class >= R700) {
sc_mode_cntl =
}
sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
- r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl,
- NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
- S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
- NULL, 0);
+ S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
- r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
S_028814_PROVOKING_VTX_LAST(prov_vtx) |
- S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
- S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+ S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
+ S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
S_028814_FACE(!state->front_ccw) |
S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
S_028814_POLY_MODE(polygon_dual_mode) |
S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
- S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)),
- NULL, 0);
-
- r600_pipe_state_add_reg(rstate, R_028034_PA_SC_SCREEN_SCISSOR_BR,
- state->rasterizer_discard ? 0 : (S_028034_BR_X(8192) | S_028034_BR_Y(8192)),
- NULL, 0);
+ S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
+ r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
return rstate;
}
{
struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
- struct r600_pipe_resource_state *rstate;
struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
unsigned format, endian;
uint32_t word4 = 0, yuv_format = 0, pitch = 0;
if (view == NULL)
return NULL;
- rstate = &view->state;
/* initialize base object */
view->base = *state;
format = r600_translate_texformat(ctx->screen, state->format,
swizzle,
&word4, &yuv_format);
+ assert(format != ~0);
if (format == ~0) {
- format = 0;
+ FREE(view);
+ return NULL;
}
if (tmp->is_depth && !tmp->is_flushing_texture) {
- r600_texture_depth_flush(ctx, texture, TRUE);
+ if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
+ FREE(view);
+ return NULL;
+ }
tmp = tmp->flushed_depth_texture;
}
depth = texture->array_size;
}
- rstate->bo[0] = &tmp->resource;
- rstate->bo[1] = &tmp->resource;
- rstate->bo_usage[0] = RADEON_USAGE_READ;
- rstate->bo_usage[1] = RADEON_USAGE_READ;
-
- rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
- S_038000_TILE_MODE(array_mode) |
- S_038000_TILE_TYPE(tile_type) |
- S_038000_PITCH((pitch / 8) - 1) |
- S_038000_TEX_WIDTH(width - 1));
- rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
- S_038004_TEX_DEPTH(depth - 1) |
- S_038004_DATA_FORMAT(format));
- rstate->val[2] = tmp->offset[offset_level] >> 8;
- rstate->val[3] = tmp->offset[offset_level+1] >> 8;
- rstate->val[4] = (word4 |
- S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
- S_038010_REQUEST_SIZE(1) |
- S_038010_ENDIAN_SWAP(endian) |
- S_038010_BASE_LEVEL(0));
- rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
- S_038014_BASE_ARRAY(state->u.tex.first_layer) |
- S_038014_LAST_ARRAY(state->u.tex.last_layer));
- rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
- S_038018_MAX_ANISO(4 /* max 16 samples */));
+ view->tex_resource = &tmp->resource;
+ view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
+ S_038000_TILE_MODE(array_mode) |
+ S_038000_TILE_TYPE(tile_type) |
+ S_038000_PITCH((pitch / 8) - 1) |
+ S_038000_TEX_WIDTH(width - 1));
+ view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
+ S_038004_TEX_DEPTH(depth - 1) |
+ S_038004_DATA_FORMAT(format));
+ view->tex_resource_words[2] = tmp->offset[offset_level] >> 8;
+ view->tex_resource_words[3] = tmp->offset[offset_level+1] >> 8;
+ view->tex_resource_words[4] = (word4 |
+ S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
+ S_038010_REQUEST_SIZE(1) |
+ S_038010_ENDIAN_SWAP(endian) |
+ S_038010_BASE_LEVEL(0));
+ view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) |
+ S_038014_BASE_ARRAY(state->u.tex.first_layer) |
+ S_038014_LAST_ARRAY(state->u.tex.last_layer));
+ view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
+ S_038018_MAX_ANISO(4 /* max 16 samples */));
} else {
width = tmp->surface.level[offset_level].npix_x;
height = tmp->surface.level[offset_level].npix_y;
break;
}
- rstate->bo[0] = &tmp->resource;
- rstate->bo[1] = &tmp->resource;
- rstate->bo_usage[0] = RADEON_USAGE_READ;
- rstate->bo_usage[1] = RADEON_USAGE_READ;
-
- rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
- S_038000_TILE_MODE(array_mode) |
- S_038000_TILE_TYPE(tile_type) |
- S_038000_PITCH((pitch / 8) - 1) |
- S_038000_TEX_WIDTH(width - 1));
- rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
- S_038004_TEX_DEPTH(depth - 1) |
- S_038004_DATA_FORMAT(format));
- rstate->val[2] = tmp->surface.level[offset_level].offset >> 8;
+ view->tex_resource = &tmp->resource;
+ view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
+ S_038000_TILE_MODE(array_mode) |
+ S_038000_TILE_TYPE(tile_type) |
+ S_038000_PITCH((pitch / 8) - 1) |
+ S_038000_TEX_WIDTH(width - 1));
+ view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
+ S_038004_TEX_DEPTH(depth - 1) |
+ S_038004_DATA_FORMAT(format));
+ view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
if (offset_level >= tmp->surface.last_level) {
- rstate->val[3] = tmp->surface.level[offset_level].offset >> 8;
+ view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
} else {
- rstate->val[3] = tmp->surface.level[offset_level + 1].offset >> 8;
+ view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
}
- rstate->val[4] = (word4 |
- S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
- S_038010_REQUEST_SIZE(1) |
- S_038010_ENDIAN_SWAP(endian) |
- S_038010_BASE_LEVEL(0));
- rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
- S_038014_BASE_ARRAY(state->u.tex.first_layer) |
- S_038014_LAST_ARRAY(state->u.tex.last_layer));
- rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
- S_038018_MAX_ANISO(4 /* max 16 samples */));
+ view->tex_resource_words[4] = (word4 |
+ S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
+ S_038010_REQUEST_SIZE(1) |
+ S_038010_ENDIAN_SWAP(endian) |
+ S_038010_BASE_LEVEL(0));
+ view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) |
+ S_038014_BASE_ARRAY(state->u.tex.first_layer) |
+ S_038014_LAST_ARRAY(state->u.tex.last_layer));
+ view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
+ S_038018_MAX_ANISO(4 /* max 16 samples */));
}
return &view->base;
}
-static void r600_set_sampler_views(struct r600_context *rctx,
- struct r600_textures_info *dst,
- unsigned count,
- struct pipe_sampler_view **views,
- void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
-{
- struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
- unsigned i;
-
- if (count)
- r600_inval_texture_cache(rctx);
-
- for (i = 0; i < count; i++) {
- if (rviews[i]) {
- if (((struct r600_resource_texture *)rviews[i]->base.texture)->is_depth)
- rctx->have_depth_texture = true;
-
- /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
- if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
- rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
- dst->samplers_dirty = true;
-
- set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
- } else {
- set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
- }
-
- pipe_sampler_view_reference(
- (struct pipe_sampler_view **)&dst->views[i],
- views[i]);
- }
-
- for (i = count; i < dst->n_views; i++) {
- if (dst->views[i]) {
- set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
- pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
- }
- }
-
- dst->n_views = count;
-}
-
static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
struct pipe_sampler_view **views)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
- r600_context_pipe_state_set_vs_resource);
+ r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
}
static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
struct pipe_sampler_view **views)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
- r600_context_pipe_state_set_ps_resource);
+ r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
}
static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable)
S_009508_DISABLE_CUBE_ANISO(1) |
S_009508_SYNC_GRADIENT(1) |
S_009508_SYNC_WALKER(1) |
- S_009508_SYNC_ALIGNER(1),
- NULL, 0);
+ S_009508_SYNC_ALIGNER(1));
free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
/* TEX_ARRAY_OVERRIDE must be set for array textures to disable
* filtering between layers.
* Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
- if (tex->views[i]) {
- if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
- tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
+ if (tex->views.views[i]) {
+ if (tex->views.views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
+ tex->views.views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
tex->is_array_sampler[i] = true;
} else {
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- struct pipe_resource * cbuf;
+ struct pipe_constant_buffer cb;
if (rstate == NULL)
return;
for (int i = 0; i < 6; i++) {
r600_pipe_state_add_reg(rstate,
R_028E20_PA_CL_UCP0_X + i * 16,
- fui(state->ucp[i][0]), NULL, 0);
+ fui(state->ucp[i][0]));
r600_pipe_state_add_reg(rstate,
R_028E24_PA_CL_UCP0_Y + i * 16,
- fui(state->ucp[i][1]) , NULL, 0);
+ fui(state->ucp[i][1]) );
r600_pipe_state_add_reg(rstate,
R_028E28_PA_CL_UCP0_Z + i * 16,
- fui(state->ucp[i][2]), NULL, 0);
+ fui(state->ucp[i][2]));
r600_pipe_state_add_reg(rstate,
R_028E2C_PA_CL_UCP0_W + i * 16,
- fui(state->ucp[i][3]), NULL, 0);
+ fui(state->ucp[i][3]));
}
free(rctx->states[R600_PIPE_STATE_CLIP]);
rctx->states[R600_PIPE_STATE_CLIP] = rstate;
r600_context_pipe_state_set(rctx, rstate);
- cbuf = pipe_user_buffer_create(ctx->screen,
- state->ucp,
- 4*4*8, /* 8*4 floats */
- PIPE_BIND_CONSTANT_BUFFER);
- r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
- pipe_resource_reference(&cbuf, NULL);
+ cb.buffer = NULL;
+ cb.user_buffer = state->ucp;
+ cb.buffer_offset = 0;
+ cb.buffer_size = 4*4*8;
+ r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
+ pipe_resource_reference(&cb.buffer, NULL);
}
static void r600_set_polygon_stipple(struct pipe_context *ctx,
tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
r600_pipe_state_add_reg(rstate,
- R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
- NULL, 0);
+ R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
r600_pipe_state_add_reg(rstate,
- R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
- NULL, 0);
+ R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
free(rctx->states[R600_PIPE_STATE_SCISSOR]);
rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
rctx->viewport = *state;
rstate->id = R600_PIPE_STATE_VIEWPORT;
- r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
+ r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
+ r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
+ r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
+ r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
+ r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
unsigned offset;
const struct util_format_description *desc;
int i;
- unsigned blend_bypass = 0, blend_clamp = 1;
+ bool blend_bypass = 0, blend_clamp = 1, alphatest_bypass;
surf = (struct r600_surface *)state->cbufs[cb];
rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
- if (rtex->is_depth)
- rctx->have_depth_fb = TRUE;
-
if (rtex->is_depth && !rtex->is_flushing_texture) {
rtex = rtex->flushed_depth_texture;
}
}
format = r600_translate_colorformat(surf->base.format);
+ assert(format != ~0);
+
swap = r600_translate_colorswap(surf->base.format);
- if(rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
+ assert(swap != ~0);
+
+ if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
endian = ENDIAN_NONE;
} else {
endian = r600_colorformat_endian_swap(format);
blend_bypass = 1;
}
+ /* Alpha-test is done on the first colorbuffer only. */
+ if (cb == 0) {
+ alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
+ if (rctx->alphatest_state.bypass != alphatest_bypass) {
+ rctx->alphatest_state.bypass = alphatest_bypass;
+ r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
+ }
+ }
+
color_info |= S_0280A0_FORMAT(format) |
S_0280A0_COMP_SWAP(swap) |
S_0280A0_BLEND_BYPASS(blend_bypass) |
ntype != V_0280A0_NUMBER_UINT &&
ntype != V_0280A0_NUMBER_SINT) &&
G_0280A0_BLEND_CLAMP(color_info) &&
- !G_0280A0_BLEND_FLOAT32(color_info))
+ !G_0280A0_BLEND_FLOAT32(color_info)) {
color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
+ } else {
+ rctx->export_16bpc = false;
+ }
} else {
/* EXPORT_NORM can be enabled if:
* - 11-bit or smaller UNORM/SNORM/SRGB
desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
(desc->channel[i].size < 17 &&
- desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
+ desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
+ } else {
+ rctx->export_16bpc = false;
+ }
}
- r600_pipe_state_add_reg(rstate,
+ /* for possible dual-src MRT write color info 1 */
+ if (cb == 0 && rctx->framebuffer.nr_cbufs == 1) {
+ r600_pipe_state_add_reg_bo(rstate,
+ R_0280A0_CB_COLOR0_INFO + 1 * 4,
+ color_info, &rtex->resource, RADEON_USAGE_READWRITE);
+ }
+
+ r600_pipe_state_add_reg_bo(rstate,
R_028040_CB_COLOR0_BASE + cb * 4,
offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg(rstate,
+ r600_pipe_state_add_reg_bo(rstate,
R_0280A0_CB_COLOR0_INFO + cb * 4,
color_info, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate,
R_028060_CB_COLOR0_SIZE + cb * 4,
S_028060_PITCH_TILE_MAX(pitch) |
- S_028060_SLICE_TILE_MAX(slice),
- NULL, 0);
+ S_028060_SLICE_TILE_MAX(slice));
if (!rscreen->use_surface_alloc) {
r600_pipe_state_add_reg(rstate,
R_028080_CB_COLOR0_VIEW + cb * 4,
- 0x00000000, NULL, 0);
+ 0x00000000);
} else {
if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
r600_pipe_state_add_reg(rstate,
R_028080_CB_COLOR0_VIEW + cb * 4,
- 0x00000000, NULL, 0);
+ 0x00000000);
} else {
r600_pipe_state_add_reg(rstate,
R_028080_CB_COLOR0_VIEW + cb * 4,
S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
- S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
- NULL, 0);
+ S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
}
}
- r600_pipe_state_add_reg(rstate,
- R_0280E0_CB_COLOR0_FRAG + cb * 4,
- 0, &rtex->resource, RADEON_USAGE_READWRITE);
- r600_pipe_state_add_reg(rstate,
- R_0280C0_CB_COLOR0_TILE + cb * 4,
- 0, &rtex->resource, RADEON_USAGE_READWRITE);
+ r600_pipe_state_add_reg_bo(rstate,
+ R_0280E0_CB_COLOR0_FRAG + cb * 4,
+ 0, &rtex->resource, RADEON_USAGE_READWRITE);
+ r600_pipe_state_add_reg_bo(rstate,
+ R_0280C0_CB_COLOR0_TILE + cb * 4,
+ 0, &rtex->resource, RADEON_USAGE_READWRITE);
}
static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
}
}
- format = r600_translate_dbformat(state->zsbuf->texture->format);
+ format = r600_translate_dbformat(state->zsbuf->format);
+ assert(format != ~0);
- r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
+ r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE,
offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
- S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
- NULL, 0);
+ S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice));
if (!rscreen->use_surface_alloc) {
- r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000);
} else {
r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW,
S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) |
- S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer),
- NULL, 0);
+ S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer));
}
- r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
+ r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO,
S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
&rtex->resource, RADEON_USAGE_READWRITE);
r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
- (surf->aligned_height / 8) - 1, NULL, 0);
+ (surf->aligned_height / 8) - 1);
}
static void r600_set_framebuffer_state(struct pipe_context *ctx,
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- uint32_t shader_mask, tl, br, shader_control;
+ uint32_t tl, br;
if (rstate == NULL)
return;
util_copy_framebuffer_state(&rctx->framebuffer, state);
/* build states */
- rctx->have_depth_fb = 0;
+ rctx->export_16bpc = true;
+ rctx->nr_cbufs = state->nr_cbufs;
+
for (int i = 0; i < state->nr_cbufs; i++) {
r600_cb(rctx, rstate, state, i);
}
r600_db(rctx, rstate, state);
}
- shader_mask = 0;
- shader_control = 0;
- for (int i = 0; i < state->nr_cbufs; i++) {
- shader_mask |= 0xf << (i * 4);
- shader_control |= 1 << i;
- }
tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
r600_pipe_state_add_reg(rstate,
- R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
- NULL, 0);
+ R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
r600_pipe_state_add_reg(rstate,
- R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
- NULL, 0);
+ R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
+ /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
+ * will assure that the alpha-test will work even if there is
+ * no colorbuffer bound. */
r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
- shader_control, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
- shader_mask, NULL, 0);
+ (1ull << MAX2(state->nr_cbufs, 1)) - 1);
+
+ if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
+ rctx->alphatest_state.bypass = false;
+ r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
+ }
free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
if (state->zsbuf) {
r600_polygon_offset_update(rctx);
}
+
+ if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
+ rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
+ r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
+ }
+}
+
+static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
+ unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
+ unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
+ unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
+
+ r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
+ r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
+ r600_write_value(cs, (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
+ r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
+ a->cb_color_control |
+ S_028808_MULTIWRITE_ENABLE(multiwrite));
}
static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->cs;
- struct r600_atom_db_misc_state *a = (struct r600_atom_db_misc_state*)atom;
+ struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
unsigned db_render_control = 0;
unsigned db_render_override =
S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
}
db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
}
- if (a->flush_depthstencil_enabled) {
+ if (a->flush_depthstencil_through_cb) {
db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(1) |
S_028D0C_STENCIL_COPY_ENABLE(1) |
S_028D0C_COPY_CENTROID(1);
r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
}
+static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
+
+ while (dirty_mask) {
+ struct pipe_vertex_buffer *vb;
+ struct r600_resource *rbuffer;
+ unsigned offset;
+ unsigned buffer_index = u_bit_scan(&dirty_mask);
+
+ vb = &rctx->vertex_buffer_state.vb[buffer_index];
+ rbuffer = (struct r600_resource*)vb->buffer;
+ assert(rbuffer);
+
+ offset = vb->buffer_offset;
+
+ /* fetch resources start at index 320 */
+ r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
+ r600_write_value(cs, (320 + buffer_index) * 7);
+ r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
+ r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
+ r600_write_value(cs, /* RESOURCEi_WORD2 */
+ S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
+ S_038008_STRIDE(vb->stride));
+ r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
+ r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
+ r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
+ r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
+
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+ r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
+ }
+}
+
+static void r600_emit_constant_buffers(struct r600_context *rctx,
+ struct r600_constbuf_state *state,
+ unsigned buffer_id_base,
+ unsigned reg_alu_constbuf_size,
+ unsigned reg_alu_const_cache)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ uint32_t dirty_mask = state->dirty_mask;
+
+ while (dirty_mask) {
+ struct pipe_constant_buffer *cb;
+ struct r600_resource *rbuffer;
+ unsigned offset;
+ unsigned buffer_index = ffs(dirty_mask) - 1;
+
+ cb = &state->cb[buffer_index];
+ rbuffer = (struct r600_resource*)cb->buffer;
+ assert(rbuffer);
+
+ offset = cb->buffer_offset;
+
+ r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
+ ALIGN_DIVUP(cb->buffer_size >> 4, 16));
+ r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
+
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+ r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
+
+ r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
+ r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
+ r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
+ r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
+ r600_write_value(cs, /* RESOURCEi_WORD2 */
+ S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
+ S_038008_STRIDE(16));
+ r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
+ r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
+ r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
+ r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
+
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+ r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
+
+ dirty_mask &= ~(1 << buffer_index);
+ }
+ state->dirty_mask = 0;
+}
+
+static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
+{
+ r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
+ R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
+ R_028980_ALU_CONST_CACHE_VS_0);
+}
+
+static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
+{
+ r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
+ R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
+ R_028940_ALU_CONST_CACHE_PS_0);
+}
+
+static void r600_emit_sampler_views(struct r600_context *rctx,
+ struct r600_samplerview_state *state,
+ unsigned resource_id_base)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ uint32_t dirty_mask = state->dirty_mask;
+
+ while (dirty_mask) {
+ struct r600_pipe_sampler_view *rview;
+ unsigned resource_index = u_bit_scan(&dirty_mask);
+ unsigned reloc;
+
+ rview = state->views[resource_index];
+ assert(rview);
+
+ r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
+ r600_write_value(cs, (resource_id_base + resource_index) * 7);
+ r600_write_array(cs, 7, rview->tex_resource_words);
+
+ /* XXX The kernel needs two relocations. This is stupid. */
+ reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
+ RADEON_USAGE_READ);
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+ r600_write_value(cs, reloc);
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+ r600_write_value(cs, reloc);
+ }
+ state->dirty_mask = 0;
+}
+
+static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
+{
+ r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS);
+}
+
+static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
+{
+ r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
+}
+
void r600_init_state_functions(struct r600_context *rctx)
{
- r600_init_atom(&rctx->atom_db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
- r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom);
+ r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0);
+ r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
+ r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
+ r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
+ r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0);
+ r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0);
+ r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0);
+ r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0);
+ r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0);
rctx->context.create_blend_state = r600_create_blend_state;
rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
- rctx->context.create_fs_state = r600_create_shader_state;
+ rctx->context.create_fs_state = r600_create_shader_state_ps;
rctx->context.create_rasterizer_state = r600_create_rs_state;
rctx->context.create_sampler_state = r600_create_sampler_state;
rctx->context.create_sampler_view = r600_create_sampler_view;
rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
- rctx->context.create_vs_state = r600_create_shader_state;
+ rctx->context.create_vs_state = r600_create_shader_state_vs;
rctx->context.bind_blend_state = r600_bind_blend_state;
rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
rctx->context.set_viewport_state = r600_set_viewport_state;
rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
- rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
rctx->context.texture_barrier = r600_texture_barrier;
rctx->context.create_stream_output_target = r600_create_so_target;
rctx->context.stream_output_target_destroy = r600_so_target_destroy;
rctx->context.set_stream_output_targets = r600_set_so_targets;
}
+/* Adjust GPR allocation on R6xx/R7xx */
void r600_adjust_gprs(struct r600_context *rctx)
{
struct r600_pipe_state rstate;
unsigned tmp;
int diff;
- if (rctx->chip_class >= EVERGREEN)
- return;
+ /* XXX: Following call moved from r600_bind_[ps|vs]_shader,
+ * it seems eg+ doesn't need it, r6xx/7xx probably need it only for
+ * adjusting the GPR allocation?
+ * Do we need this if we aren't really changing config below? */
+ r600_inval_shader_cache(rctx);
- if (!rctx->ps_shader || !rctx->vs_shader)
- return;
-
- if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
+ if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs)
{
- diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
+ diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
num_vs_gprs -= diff;
num_ps_gprs += diff;
}
- if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
+ if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
{
- diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
+ diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
num_ps_gprs -= diff;
num_vs_gprs += diff;
}
tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
rstate.nregs = 0;
- r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0);
+ r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
r600_context_pipe_state_set(rctx, &rstate);
}
int num_gs_stack_entries;
int num_es_stack_entries;
enum radeon_family family;
- struct r600_command_buffer *cb = &rctx->atom_start_cs;
+ struct r600_command_buffer *cb = &rctx->start_cs_cmd;
uint32_t tmp;
unsigned i;
r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
- r600_store_context_reg(cb, R_028350_SX_MISC, 0);
-
if (rctx->chip_class >= R700) {
r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF);
- r600_store_context_reg(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
+ r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
+ r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
+ r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
- if (rctx->chip_class == R700)
+ if (rctx->chip_class == R700 && rctx->screen->has_streamout)
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
+ if (rctx->screen->has_streamout) {
+ r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
+ }
r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
int pos_index = -1, face_index = -1;
unsigned tmp, sid, ufi = 0;
int need_linear = 0;
+ unsigned z_export = 0, stencil_export = 0;
rstate->nregs = 0;
}
r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
- tmp, NULL, 0);
+ tmp);
}
db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
for (i = 0; i < rshader->noutput; i++) {
if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
- db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
+ z_export = 1;
if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
- db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
+ stencil_export = 1;
}
+ db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
+ db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
if (rshader->uses_kill)
db_shader_control |= S_02880C_KILL_ENABLE(1);
exports_ps = 0;
- num_cout = 0;
for (i = 0; i < rshader->noutput; i++) {
if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
- rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
+ rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
exports_ps |= 1;
- else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
- num_cout++;
}
}
+ num_cout = rshader->nr_ps_color_exports;
exports_ps |= S_028854_EXPORT_COLORS(num_cout);
if (!exports_ps) {
/* always at least export 1 component per pixel */
exports_ps = 2;
}
+ shader->nr_ps_color_outputs = num_cout;
+
spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
S_0286CC_PERSP_GRADIENT_ENA(1)|
S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
if (rctx->family == CHIP_R600)
ufi = 1;
- r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, NULL, 0);
- r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
- r600_pipe_state_add_reg(rstate,
- R_028840_SQ_PGM_START_PS,
- 0, shader->bo, RADEON_USAGE_READ);
+ r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
+ r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
+ r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
+ r600_pipe_state_add_reg_bo(rstate,
+ R_028840_SQ_PGM_START_PS,
+ 0, shader->bo, RADEON_USAGE_READ);
r600_pipe_state_add_reg(rstate,
R_028850_SQ_PGM_RESOURCES_PS,
S_028850_NUM_GPRS(rshader->bc.ngpr) |
S_028850_STACK_SIZE(rshader->bc.nstack) |
- S_028850_UNCACHED_FIRST_INST(ufi),
- NULL, 0);
+ S_028850_UNCACHED_FIRST_INST(ufi));
r600_pipe_state_add_reg(rstate,
R_028854_SQ_PGM_EXPORTS_PS,
- exports_ps, NULL, 0);
+ exports_ps);
/* only set some bits here, the other bits are set in the dsa state */
- r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
- db_shader_control,
- NULL, 0);
+ shader->db_shader_control = db_shader_control;
+ shader->ps_depth_export = z_export | stencil_export;
shader->sprite_coord_enable = rctx->sprite_coord_enable;
if (rctx->rasterizer)
for (i = 0; i < 10; i++) {
r600_pipe_state_add_reg(rstate,
R_028614_SPI_VS_OUT_ID_0 + i * 4,
- spi_vs_out_id[i], NULL, 0);
+ spi_vs_out_id[i]);
}
/* Certain attributes (position, psize, etc.) don't count as params.
nparams = 1;
r600_pipe_state_add_reg(rstate,
- R_0286C4_SPI_VS_OUT_CONFIG,
- S_0286C4_VS_EXPORT_COUNT(nparams - 1),
- NULL, 0);
- r600_pipe_state_add_reg(rstate,
- R_028868_SQ_PGM_RESOURCES_VS,
- S_028868_NUM_GPRS(rshader->bc.ngpr) |
- S_028868_STACK_SIZE(rshader->bc.nstack),
- NULL, 0);
+ R_0286C4_SPI_VS_OUT_CONFIG,
+ S_0286C4_VS_EXPORT_COUNT(nparams - 1));
r600_pipe_state_add_reg(rstate,
+ R_028868_SQ_PGM_RESOURCES_VS,
+ S_028868_NUM_GPRS(rshader->bc.ngpr) |
+ S_028868_STACK_SIZE(rshader->bc.nstack));
+ r600_pipe_state_add_reg_bo(rstate,
R_028858_SQ_PGM_START_VS,
0, shader->bo, RADEON_USAGE_READ);
rstate = &ve->rstate;
rstate->id = R600_PIPE_STATE_FETCH_SHADER;
rstate->nregs = 0;
- r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
+ r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
0,
ve->fetch_shader, RADEON_USAGE_READ);
}
void *r600_create_db_flush_dsa(struct r600_context *rctx)
{
struct pipe_depth_stencil_alpha_state dsa;
- struct r600_pipe_state *rstate;
- struct r600_pipe_dsa *dsa_state;
boolean quirk = false;
if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
dsa.stencil[0].writemask = 0xff;
}
- rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
- dsa_state = (struct r600_pipe_dsa*)rstate;
- dsa_state->is_flush = true;
- return rstate;
+ return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
}
-void r600_pipe_init_buffer_resource(struct r600_context *rctx,
- struct r600_pipe_resource_state *rstate)
+void r600_update_dual_export_state(struct r600_context * rctx)
{
- rstate->id = R600_PIPE_STATE_RESOURCE;
-
- rstate->bo[0] = NULL;
- rstate->val[0] = 0;
- rstate->val[1] = 0;
- rstate->val[2] = 0;
- rstate->val[3] = 0;
- rstate->val[4] = 0;
- rstate->val[5] = 0;
- rstate->val[6] = 0xc0000000;
-}
+ unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
+ !rctx->ps_shader->current->ps_depth_export;
+ unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
+ S_02880C_DUAL_EXPORT_ENABLE(dual_export);
-void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
- struct r600_resource *rbuffer,
- unsigned offset, unsigned stride,
- enum radeon_bo_usage usage)
-{
- rstate->val[0] = offset;
- rstate->bo[0] = rbuffer;
- rstate->bo_usage[0] = usage;
- rstate->val[1] = rbuffer->buf->size - offset - 1;
- rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
- S_038008_STRIDE(stride);
+ if (db_shader_control != rctx->db_shader_control) {
+ struct r600_pipe_state rstate;
+
+ rctx->db_shader_control = db_shader_control;
+ rstate.nregs = 0;
+ r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
+ r600_context_pipe_state_set(rctx, &rstate);
+ }
}
projects / mesa.git / blobdiff