r600g: make F2U trans-only on r600-r700

[mesa.git] / src / gallium / drivers / r600 / r600_state.c

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index c1061ddbe0c8dfd46bceaf812fef32f3f1fc8656..d06c25000f18608dc171722765b5d686f16e98eb 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -753,6 +753,15 @@ static void *r600_create_blend_state(struct pipe_context *ctx,
                if (i == 0)
                        r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
        }
+
+       r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK,
+                               S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
+                               S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
+                               S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
+                               S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
+                               S_028D44_ALPHA_TO_MASK_OFFSET3(2));
+
+       blend->alpha_to_one = state->alpha_to_one;
        return rstate;
 }
 
@@ -846,6 +855,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
                S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
                S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
                S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
+       rs->multisample_enable = state->multisample;
 
        /* offset */
        rs->offset_units = state->offset_units;
@@ -969,7 +979,7 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
                                                        const struct pipe_sampler_view *state)
 {
        struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
-       struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
+       struct r600_texture *tmp = (struct r600_texture*)texture;
        unsigned format, endian;
        uint32_t word4 = 0, yuv_format = 0, pitch = 0;
        unsigned char swizzle[4], array_mode = 0, tile_type = 0;
@@ -1071,15 +1081,13 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
                                      struct pipe_sampler_view **views)
 {
-       struct r600_context *rctx = (struct r600_context *)ctx;
-       r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
+       r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
 }
 
 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
                                      struct pipe_sampler_view **views)
 {
-       struct r600_context *rctx = (struct r600_context *)ctx;
-       r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
+       r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
 }
 
 static void r600_set_clip_state(struct pipe_context *ctx,
@@ -1126,10 +1134,6 @@ static void r600_set_polygon_stipple(struct pipe_context *ctx,
 {
 }
 
-static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
-{
-}
-
 void r600_set_scissor_state(struct r600_context *rctx,
                            const struct pipe_scissor_state *state)
 {
@@ -1193,7 +1197,7 @@ static void r600_set_viewport_state(struct pipe_context *ctx,
 static void r600_init_color_surface(struct r600_context *rctx,
                                    struct r600_surface *surf)
 {
-       struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
+       struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
        unsigned level = surf->base.u.tex.level;
        unsigned pitch, slice;
        unsigned color_info;
@@ -1341,7 +1345,7 @@ static void r600_init_color_surface(struct r600_context *rctx,
 static void r600_init_depth_surface(struct r600_context *rctx,
                                    struct r600_surface *surf)
 {
-       struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
+       struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
        unsigned level, pitch, slice, format, offset, array_mode;
 
        level = surf->base.u.tex.level;
@@ -1398,6 +1402,8 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
        /* build states */
        rctx->export_16bpc = true;
        rctx->nr_cbufs = state->nr_cbufs;
+       rctx->cb0_is_integer = state->nr_cbufs &&
+                              util_format_is_pure_integer(state->cbufs[0]->format);
 
        for (i = 0; i < state->nr_cbufs; i++) {
                surf = (struct r600_surface*)state->cbufs[i];
@@ -1430,6 +1436,9 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
                                           surf->cb_color_info, res, RADEON_USAGE_READWRITE);
                i++;
        }
+       for (; i < 8 ; i++) {
+               r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 0);
+       }
 
        /* Update alpha-test state dependencies.
         * Alpha-test is done on the first colorbuffer only. */
@@ -1742,6 +1751,15 @@ static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_a
        r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
 }
 
+static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
+{
+       struct r600_sample_mask *s = (struct r600_sample_mask*)a;
+       uint8_t mask = s->sample_mask;
+
+       r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
+                              mask | (mask << 8) | (mask << 16) | (mask << 24));
+}
+
 void r600_init_state_functions(struct r600_context *rctx)
 {
        r600_init_atom(&rctx->seamless_cube_map.atom, r600_emit_seamless_cube_map, 3, 0);
@@ -1761,6 +1779,10 @@ void r600_init_state_functions(struct r600_context *rctx)
        r600_init_atom(&rctx->vs_samplers.atom_sampler, r600_emit_vs_sampler, 0, EMIT_EARLY);
        r600_init_atom(&rctx->ps_samplers.atom_sampler, r600_emit_ps_sampler, 0, EMIT_EARLY);
 
+       r600_init_atom(&rctx->sample_mask.atom, r600_emit_sample_mask, 3, 0);
+       rctx->sample_mask.sample_mask = ~0;
+       r600_atom_dirty(rctx, &rctx->sample_mask.atom);
+
        rctx->context.create_blend_state = r600_create_blend_state;
        rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
        rctx->context.create_fs_state = r600_create_shader_state_ps;
@@ -2115,8 +2137,6 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
        r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
        r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
 
-       r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00);
-
        r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
        r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
 
@@ -2156,8 +2176,6 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
        r600_store_value(cb, 0xFF);       /* R_028C38_CB_CLRCMP_DST */
        r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
 
-       r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF);
-
        r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
        r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
        r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */