#include "r600_shader.h"
#include "r600d.h"
-#include "util/u_draw_quad.h"
#include "util/u_format_s3tc.h"
#include "util/u_index_modify.h"
#include "util/u_memory.h"
#include "util/u_math.h"
#include "tgsi/tgsi_parse.h"
-#define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
-
void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
{
assert(!cb->buf);
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_blend_state *blend = (struct r600_blend_state *)state;
- if (blend == NULL)
+ if (blend == NULL) {
+ r600_set_cso_state_with_cb(&rctx->blend_state, NULL, NULL);
return;
+ }
r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
}
/* Workaround for a missing scissor enable on r600. */
if (rctx->b.chip_class == R600 &&
- rs->scissor_enable != rctx->scissor.enable) {
- rctx->scissor.enable = rs->scissor_enable;
- rctx->scissor.atom.dirty = true;
+ rs->scissor_enable != rctx->scissor[0].enable) {
+ rctx->scissor[0].enable = rs->scissor_enable;
+ rctx->scissor[0].atom.dirty = true;
}
/* Re-emit PA_SC_LINE_STIPPLE. */
static void r600_sampler_view_destroy(struct pipe_context *ctx,
struct pipe_sampler_view *state)
{
- struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
+ struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
+
+ if (view->tex_resource->gpu_address &&
+ view->tex_resource->b.b.target == PIPE_BUFFER)
+ LIST_DELINIT(&view->list);
pipe_resource_reference(&state->texture, NULL);
- FREE(resource);
+ FREE(view);
}
void r600_sampler_states_dirty(struct r600_context *rctx,
static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
{
+ struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_blend_state *blend = (struct r600_blend_state*)state;
+ if (rctx->blend_state.cso == state) {
+ ctx->bind_blend_state(ctx, NULL);
+ }
+
r600_release_command_buffer(&blend->buffer);
r600_release_command_buffer(&blend->buffer_no_blend);
FREE(blend);
dst->views.dirty_mask |= new_mask;
dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
- dst->views.dirty_txq_constants = TRUE;
dst->views.dirty_buffer_constants = TRUE;
r600_sampler_views_dirty(rctx, &dst->views);
const struct pipe_viewport_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
+ int i;
- rctx->viewport.state = *state;
- rctx->viewport.atom.dirty = true;
+ for (i = start_slot; i < start_slot + num_viewports; i++) {
+ rctx->viewport[i].state = state[i - start_slot];
+ rctx->viewport[i].atom.dirty = true;
+ }
}
void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
- struct pipe_viewport_state *state = &rctx->viewport.state;
+ struct r600_viewport_state *rstate = (struct r600_viewport_state *)atom;
+ struct pipe_viewport_state *state = &rstate->state;
+ int offset = rstate->idx * 6 * 4;
- r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
+ r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0 + offset, 6);
radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
}
for (i = 0; i < size / 4; ++i) {
- tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
+ tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
}
u_upload_data(rctx->b.uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
* then in the shader, we AND the 4 components with 0xffffffff or 0,
* then OR the alpha with the value given here.
* We use a 6th constant to store the txq buffer size in
+ * we use 7th slot for number of cube layers in a cube map array.
*/
static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
{
samplers->buffer_constants[offset + 4] = 0;
samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
+ samplers->buffer_constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
}
}
pipe_resource_reference(&cb.buffer, NULL);
}
-/* On evergreen we only need to store the buffer size for TXQ */
+/* On evergreen we store two values
+ * 1. buffer size for TXQ
+ * 2. number of cube layers in a cube map array.
+ */
static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
{
struct r600_textures_info *samplers = &rctx->samplers[shader_type];
samplers->views.dirty_buffer_constants = FALSE;
bits = util_last_bit(samplers->views.enabled_mask);
- array_size = bits * sizeof(uint32_t) * 4;
+ array_size = bits * 2 * sizeof(uint32_t) * 4;
samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
memset(samplers->buffer_constants, 0, array_size);
- for (i = 0; i < bits; i++)
- if (samplers->views.enabled_mask & (1 << i))
- samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
+ for (i = 0; i < bits; i++) {
+ if (samplers->views.enabled_mask & (1 << i)) {
+ uint32_t offset = i * 2;
+ samplers->buffer_constants[offset] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
+ samplers->buffer_constants[offset + 1] = samplers->views.views[i]->base.texture->array_size / 6;
+ }
+ }
cb.buffer = NULL;
cb.user_buffer = samplers->buffer_constants;
pipe_resource_reference(&cb.buffer, NULL);
}
-static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
+/* set sample xy locations as array of fragment shader constants */
+void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
{
- struct r600_textures_info *samplers = &rctx->samplers[shader_type];
- int bits;
- uint32_t array_size;
- struct pipe_constant_buffer cb;
+ struct pipe_constant_buffer constbuf = {0};
+ float values[4*16] = {0.0f};
int i;
+ struct pipe_context *ctx = &rctx->b.b;
- if (!samplers->views.dirty_txq_constants)
- return;
-
- samplers->views.dirty_txq_constants = FALSE;
-
- bits = util_last_bit(samplers->views.enabled_mask);
- array_size = bits * sizeof(uint32_t) * 4;
- samplers->txq_constants = realloc(samplers->txq_constants, array_size);
- memset(samplers->txq_constants, 0, array_size);
- for (i = 0; i < bits; i++)
- if (samplers->views.enabled_mask & (1 << i))
- samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
+ assert(rctx->framebuffer.nr_samples <= Elements(values)/4);
+ for (i = 0; i < rctx->framebuffer.nr_samples; i++) {
+ ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &values[4*i]);
+ /* Also fill in center-zeroed positions used for interpolateAtSample */
+ values[4*i + 2] = values[4*i + 0] - 0.5f;
+ values[4*i + 3] = values[4*i + 1] - 0.5f;
+ }
- cb.buffer = NULL;
- cb.user_buffer = samplers->txq_constants;
- cb.buffer_offset = 0;
- cb.buffer_size = array_size;
- rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_TXQ_CONST_BUFFER, &cb);
- pipe_resource_reference(&cb.buffer, NULL);
+ constbuf.user_buffer = values;
+ constbuf.buffer_size = rctx->framebuffer.nr_samples * 4 * 4;
+ ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
+ R600_SAMPLE_POSITIONS_CONST_BUFFER, &constbuf);
+ pipe_resource_reference(&constbuf.buffer, NULL);
}
static void update_shader_atom(struct pipe_context *ctx,
unsigned size = 0x1C000;
rctx->gs_rings.esgs_ring.buffer =
pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_STATIC, size);
+ PIPE_USAGE_DEFAULT, size);
rctx->gs_rings.esgs_ring.buffer_size = size;
size = 0x4000000;
rctx->gs_rings.gsvs_ring.buffer =
pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_STATIC, size);
+ PIPE_USAGE_DEFAULT, size);
rctx->gs_rings.gsvs_ring.buffer_size = size;
}
struct pipe_context * ctx = (struct pipe_context*)rctx;
bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
bool blend_disable;
-
+ bool need_buf_const;
if (!rctx->blitter->running) {
unsigned i;
if (unlikely(!rctx->gs_shader->current))
return false;
- if (rctx->b.chip_class >= EVERGREEN && !rctx->shader_stages.geom_enable) {
+ if (!rctx->shader_stages.geom_enable) {
rctx->shader_stages.geom_enable = true;
rctx->shader_stages.atom.dirty = true;
}
if (unlikely(rctx->geometry_shader.shader != rctx->gs_shader->current)) {
update_shader_atom(ctx, &rctx->geometry_shader, rctx->gs_shader->current);
update_shader_atom(ctx, &rctx->vertex_shader, rctx->gs_shader->current->gs_copy_shader);
+ /* Update clip misc state. */
+ if (rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
+ rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
+ rctx->clip_misc_state.clip_disable != rctx->gs_shader->current->shader.vs_position_window_space) {
+ rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl;
+ rctx->clip_misc_state.clip_dist_write = rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write;
+ rctx->clip_misc_state.clip_disable = rctx->gs_shader->current->shader.vs_position_window_space;
+ rctx->clip_misc_state.atom.dirty = true;
+ }
}
r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
/* Update clip misc state. */
if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
- rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
+ rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
+ rctx->clip_misc_state.clip_disable != rctx->vs_shader->current->shader.vs_position_window_space) {
rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
+ rctx->clip_misc_state.clip_disable = rctx->vs_shader->current->shader.vs_position_window_space;
rctx->clip_misc_state.atom.dirty = true;
}
}
if (unlikely(!rctx->ps_shader->current))
return false;
- if (unlikely(ps_dirty || rctx->pixel_shader.shader != rctx->ps_shader->current)) {
+ if (unlikely(ps_dirty || rctx->pixel_shader.shader != rctx->ps_shader->current ||
+ rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
+ rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
}
}
- if (rctx->b.chip_class >= EVERGREEN) {
- evergreen_update_db_shader_control(rctx);
- } else {
- r600_update_db_shader_control(rctx);
- }
-
if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
(rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
update_shader_atom(ctx, &rctx->pixel_shader, rctx->ps_shader->current);
}
+ if (rctx->b.chip_class >= EVERGREEN) {
+ evergreen_update_db_shader_control(rctx);
+ } else {
+ r600_update_db_shader_control(rctx);
+ }
+
/* on R600 we stuff masks + txq info into one constant buffer */
/* on evergreen we only need a txq info one */
- if (rctx->b.chip_class < EVERGREEN) {
- if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
- r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
- if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
- r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
- } else {
- if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
- eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
- if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
- eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
+ if (rctx->ps_shader) {
+ need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
+ if (need_buf_const) {
+ if (rctx->b.chip_class < EVERGREEN)
+ r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
+ else
+ eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
+ }
}
+ if (rctx->vs_shader) {
+ need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
+ if (need_buf_const) {
+ if (rctx->b.chip_class < EVERGREEN)
+ r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
+ else
+ eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
+ }
+ }
- if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
- r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
- if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
- r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
+ if (rctx->gs_shader) {
+ need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
+ if (need_buf_const) {
+ if (rctx->b.chip_class < EVERGREEN)
+ r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
+ else
+ eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
+ }
+ }
if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
if (!r600_adjust_gprs(rctx)) {
return true;
}
-static unsigned r600_conv_prim_to_gs_out(unsigned mode)
-{
- static const int prim_conv[] = {
- V_028A6C_OUTPRIM_TYPE_POINTLIST,
- V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP
- };
- assert(mode < Elements(prim_conv));
-
- return prim_conv[mode];
-}
-
void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
state->pa_cl_clip_cntl |
- (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
+ (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
+ S_028810_CLIP_DISABLE(state->clip_disable));
r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
state->pa_cl_vs_out_cntl |
(state->clip_plane_enable & state->clip_dist_write));
struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
if (!info.count && (info.indexed || !info.count_from_stream_output)) {
- assert(0);
return;
}
}
/* make sure that the gfx ring is only one active */
- if (rctx->b.rings.dma.cs) {
- rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
+ if (rctx->b.rings.dma.cs && rctx->b.rings.dma.cs->cdw) {
+ rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
}
if (!r600_update_derived_state(rctx)) {
r600_emit_atom(rctx, rctx->atoms[i]);
}
+ if (rctx->b.chip_class == CAYMAN) {
+ /* Copied from radeonsi. */
+ unsigned primgroup_size = 128; /* recommended without a GS */
+ bool ia_switch_on_eop = false;
+ bool partial_vs_wave = false;
+
+ if (rctx->gs_shader)
+ primgroup_size = 64; /* recommended with a GS */
+
+ if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
+ (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
+ ia_switch_on_eop = true;
+ }
+
+ if (rctx->b.streamout.streamout_enabled ||
+ rctx->b.streamout.prims_gen_query_enabled)
+ partial_vs_wave = true;
+
+ r600_write_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
+ S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
+ S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
+ S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
+ }
+
+ /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
+ * even though it should have no effect on those. */
+ if (rctx->b.chip_class == R600 && rctx->rasterizer) {
+ unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
+ unsigned prim = info.mode;
+
+ if (rctx->gs_shader) {
+ prim = rctx->gs_shader->current->shader.gs_output_prim;
+ }
+ prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
+
+ if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
+ prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
+ info.mode == R600_PRIM_RECTANGLE_LIST) {
+ su_sc_mode_cntl &= C_028814_CULL_FRONT;
+ }
+ r600_write_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
+ }
+
/* Update start instance. */
if (rctx->last_start_instance != info.start_instance) {
r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
S_028A0C_AUTO_RESET_CNTL(ls_mask) |
(rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
- r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
- r600_conv_prim_to_gs_out(info.mode));
r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
r600_conv_pipe_prim(info.mode));
memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
cs->cdw += size_dw;
} else {
- uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
+ uint64_t va = r600_resource(ib.buffer)->gpu_address + ib.offset;
cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->b.predicate_drawing);
cs->buf[cs->cdw++] = va;
cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
cs->buf[cs->cdw++] = info.count;
cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
- cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
+ cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+ (struct r600_resource*)ib.buffer,
+ RADEON_USAGE_READ, RADEON_PRIO_MIN);
}
} else {
if (info.count_from_stream_output) {
struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
- uint64_t va = r600_resource_va(&rctx->screen->b.b, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
+ uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
cs->buf[cs->cdw++] = 0; /* unused */
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
- cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
+ cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+ t->buf_filled_size, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
}
cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->b.predicate_drawing);
rctx->b.num_draw_calls++;
}
-void r600_draw_rectangle(struct blitter_context *blitter,
- int x1, int y1, int x2, int y2, float depth,
- enum blitter_attrib_type type, const union pipe_color_union *attrib)
-{
- struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
- struct pipe_viewport_state viewport;
- struct pipe_resource *buf = NULL;
- unsigned offset = 0;
- float *vb;
-
- if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
- util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
- return;
- }
-
- /* Some operations (like color resolve on r6xx) don't work
- * with the conventional primitive types.
- * One that works is PT_RECTLIST, which we use here. */
-
- /* setup viewport */
- viewport.scale[0] = 1.0f;
- viewport.scale[1] = 1.0f;
- viewport.scale[2] = 1.0f;
- viewport.scale[3] = 1.0f;
- viewport.translate[0] = 0.0f;
- viewport.translate[1] = 0.0f;
- viewport.translate[2] = 0.0f;
- viewport.translate[3] = 0.0f;
- rctx->b.b.set_viewport_states(&rctx->b.b, 0, 1, &viewport);
-
- /* Upload vertices. The hw rectangle has only 3 vertices,
- * I guess the 4th one is derived from the first 3.
- * The vertex specification should match u_blitter's vertex element state. */
- u_upload_alloc(rctx->b.uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
- vb[0] = x1;
- vb[1] = y1;
- vb[2] = depth;
- vb[3] = 1;
-
- vb[8] = x1;
- vb[9] = y2;
- vb[10] = depth;
- vb[11] = 1;
-
- vb[16] = x2;
- vb[17] = y1;
- vb[18] = depth;
- vb[19] = 1;
-
- if (attrib) {
- memcpy(vb+4, attrib->f, sizeof(float)*4);
- memcpy(vb+12, attrib->f, sizeof(float)*4);
- memcpy(vb+20, attrib->f, sizeof(float)*4);
- }
-
- /* draw */
- util_draw_vertex_buffer(&rctx->b.b, NULL, buf, rctx->blitter->vb_slot, offset,
- R600_PRIM_RECTANGLE_LIST, 3, 2);
- pipe_resource_reference(&buf, NULL);
-}
-
uint32_t r600_translate_stencil_op(int s_op)
{
switch (s_op) {
r600_emit_command_buffer(cs, &shader->command_buffer);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo, RADEON_USAGE_READ));
-}
-
-struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
- struct pipe_resource *texture,
- const struct pipe_surface *templ,
- unsigned width, unsigned height)
-{
- struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
-
- assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
- assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
- assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
- if (surface == NULL)
- return NULL;
- pipe_reference_init(&surface->base.reference, 1);
- pipe_resource_reference(&surface->base.texture, texture);
- surface->base.context = pipe;
- surface->base.format = templ->format;
- surface->base.width = width;
- surface->base.height = height;
- surface->base.u = templ->u;
- return &surface->base;
-}
-
-static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
- struct pipe_resource *tex,
- const struct pipe_surface *templ)
-{
- unsigned level = templ->u.tex.level;
-
- return r600_create_surface_custom(pipe, tex, templ,
- u_minify(tex->width0, level),
- u_minify(tex->height0, level));
-}
-
-static void r600_surface_destroy(struct pipe_context *pipe,
- struct pipe_surface *surface)
-{
- struct r600_surface *surf = (struct r600_surface*)surface;
- pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
- pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
- pipe_resource_reference(&surface->texture, NULL);
- FREE(surface);
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo,
+ RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
}
unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
}
}
+ if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
+ if (!enable_s3tc)
+ goto out_unknown;
+
+ if (rscreen->b.chip_class < EVERGREEN)
+ goto out_unknown;
+
+ switch (format) {
+ case PIPE_FORMAT_BPTC_RGBA_UNORM:
+ case PIPE_FORMAT_BPTC_SRGBA:
+ result = FMT_BC7;
+ is_srgb_valid = TRUE;
+ goto out_word4;
+ case PIPE_FORMAT_BPTC_RGB_FLOAT:
+ word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
+ /* fall through */
+ case PIPE_FORMAT_BPTC_RGB_UFLOAT:
+ result = FMT_BC6;
+ goto out_word4;
+ default:
+ goto out_unknown;
+ }
+ }
+
if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
switch (format) {
case PIPE_FORMAT_R8G8_B8G8_UNORM:
return ~0;
}
+uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format)
+{
+ const struct util_format_description *desc = util_format_description(format);
+ int channel = util_format_get_first_non_void_channel(format);
+ bool is_float;
+
+#define HAS_SIZE(x,y,z,w) \
+ (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
+ desc->channel[2].size == (z) && desc->channel[3].size == (w))
+
+ if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
+ return V_0280A0_COLOR_10_11_11_FLOAT;
+
+ if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
+ channel == -1)
+ return ~0U;
+
+ is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
+
+ switch (desc->nr_channels) {
+ case 1:
+ switch (desc->channel[0].size) {
+ case 8:
+ return V_0280A0_COLOR_8;
+ case 16:
+ if (is_float)
+ return V_0280A0_COLOR_16_FLOAT;
+ else
+ return V_0280A0_COLOR_16;
+ case 32:
+ if (is_float)
+ return V_0280A0_COLOR_32_FLOAT;
+ else
+ return V_0280A0_COLOR_32;
+ }
+ break;
+ case 2:
+ if (desc->channel[0].size == desc->channel[1].size) {
+ switch (desc->channel[0].size) {
+ case 4:
+ if (chip <= R700)
+ return V_0280A0_COLOR_4_4;
+ else
+ return ~0U; /* removed on Evergreen */
+ case 8:
+ return V_0280A0_COLOR_8_8;
+ case 16:
+ if (is_float)
+ return V_0280A0_COLOR_16_16_FLOAT;
+ else
+ return V_0280A0_COLOR_16_16;
+ case 32:
+ if (is_float)
+ return V_0280A0_COLOR_32_32_FLOAT;
+ else
+ return V_0280A0_COLOR_32_32;
+ }
+ } else if (HAS_SIZE(8,24,0,0)) {
+ return V_0280A0_COLOR_24_8;
+ } else if (HAS_SIZE(24,8,0,0)) {
+ return V_0280A0_COLOR_8_24;
+ }
+ break;
+ case 3:
+ if (HAS_SIZE(5,6,5,0)) {
+ return V_0280A0_COLOR_5_6_5;
+ } else if (HAS_SIZE(32,8,24,0)) {
+ return V_0280A0_COLOR_X24_8_32_FLOAT;
+ }
+ break;
+ case 4:
+ if (desc->channel[0].size == desc->channel[1].size &&
+ desc->channel[0].size == desc->channel[2].size &&
+ desc->channel[0].size == desc->channel[3].size) {
+ switch (desc->channel[0].size) {
+ case 4:
+ return V_0280A0_COLOR_4_4_4_4;
+ case 8:
+ return V_0280A0_COLOR_8_8_8_8;
+ case 16:
+ if (is_float)
+ return V_0280A0_COLOR_16_16_16_16_FLOAT;
+ else
+ return V_0280A0_COLOR_16_16_16_16;
+ case 32:
+ if (is_float)
+ return V_0280A0_COLOR_32_32_32_32_FLOAT;
+ else
+ return V_0280A0_COLOR_32_32_32_32;
+ }
+ } else if (HAS_SIZE(5,5,5,1)) {
+ return V_0280A0_COLOR_1_5_5_5;
+ } else if (HAS_SIZE(10,10,10,2)) {
+ return V_0280A0_COLOR_2_10_10_10;
+ }
+ break;
+ }
+ return ~0U;
+}
+
+uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
+{
+ if (R600_BIG_ENDIAN) {
+ switch(colorformat) {
+ /* 8-bit buffers. */
+ case V_0280A0_COLOR_4_4:
+ case V_0280A0_COLOR_8:
+ return ENDIAN_NONE;
+
+ /* 16-bit buffers. */
+ case V_0280A0_COLOR_5_6_5:
+ case V_0280A0_COLOR_1_5_5_5:
+ case V_0280A0_COLOR_4_4_4_4:
+ case V_0280A0_COLOR_16:
+ case V_0280A0_COLOR_8_8:
+ return ENDIAN_8IN16;
+
+ /* 32-bit buffers. */
+ case V_0280A0_COLOR_8_8_8_8:
+ case V_0280A0_COLOR_2_10_10_10:
+ case V_0280A0_COLOR_8_24:
+ case V_0280A0_COLOR_24_8:
+ case V_0280A0_COLOR_32_FLOAT:
+ case V_0280A0_COLOR_16_16_FLOAT:
+ case V_0280A0_COLOR_16_16:
+ return ENDIAN_8IN32;
+
+ /* 64-bit buffers. */
+ case V_0280A0_COLOR_16_16_16_16:
+ case V_0280A0_COLOR_16_16_16_16_FLOAT:
+ return ENDIAN_8IN16;
+
+ case V_0280A0_COLOR_32_32_FLOAT:
+ case V_0280A0_COLOR_32_32:
+ case V_0280A0_COLOR_X24_8_32_FLOAT:
+ return ENDIAN_8IN32;
+
+ /* 128-bit buffers. */
+ case V_0280A0_COLOR_32_32_32_32_FLOAT:
+ case V_0280A0_COLOR_32_32_32_32:
+ return ENDIAN_8IN32;
+ default:
+ return ENDIAN_NONE; /* Unsupported. */
+ }
+ } else {
+ return ENDIAN_NONE;
+ }
+}
+
static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
{
struct r600_context *rctx = (struct r600_context*)ctx;
struct r600_resource *rbuffer = r600_resource(buf);
unsigned i, shader, mask, alignment = rbuffer->buf->alignment;
+ struct r600_pipe_sampler_view *view;
- /* Discard the buffer. */
- pb_reference(&rbuffer->buf, NULL);
-
- /* Create a new one in the same pipe_resource. */
- r600_init_resource(&rctx->screen->b, rbuffer, rbuffer->b.b.width0, alignment,
- TRUE, rbuffer->b.b.usage);
+ /* Reallocate the buffer in the same pipe_resource. */
+ r600_init_resource(&rctx->screen->b, rbuffer, rbuffer->b.b.width0,
+ alignment, TRUE);
/* We changed the buffer, now we need to bind it where the old one was bound. */
/* Vertex buffers. */
}
}
- /* XXX TODO: texture buffer objects */
+ /* Texture buffer objects - update the virtual addresses in descriptors. */
+ LIST_FOR_EACH_ENTRY(view, &rctx->b.texture_buffers, list) {
+ if (view->base.texture == &rbuffer->b.b) {
+ unsigned stride = util_format_get_blocksize(view->base.format);
+ uint64_t offset = (uint64_t)view->base.u.buf.first_element * stride;
+ uint64_t va = rbuffer->gpu_address + offset;
+
+ view->tex_resource_words[0] = va;
+ view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
+ view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
+ }
+ }
+ /* Texture buffer objects - make bindings dirty if needed. */
+ for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
+ struct r600_samplerview_state *state = &rctx->samplers[shader].views;
+ bool found = false;
+ uint32_t mask = state->enabled_mask;
+
+ while (mask) {
+ unsigned i = u_bit_scan(&mask);
+ if (state->views[i]->base.texture == &rbuffer->b.b) {
+ found = true;
+ state->dirty_mask |= 1 << i;
+ }
+ }
+ if (found) {
+ r600_sampler_views_dirty(rctx, state);
+ }
+ }
}
static void r600_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
rctx->b.b.texture_barrier = r600_texture_barrier;
rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
- rctx->b.b.create_surface = r600_create_surface;
- rctx->b.b.surface_destroy = r600_surface_destroy;
rctx->b.b.draw_vbo = r600_draw_vbo;
rctx->b.invalidate_buffer = r600_invalidate_buffer;
rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
uint64_t va;
uint32_t reloc;
- va = r600_resource_va(&rscreen->b.b, (void*)rscreen->b.trace_bo);
- reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo, RADEON_USAGE_READWRITE);
+ va = rscreen->b.trace_bo->gpu_address;
+ reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
radeon_emit(cs, va & 0xFFFFFFFFUL);
radeon_emit(cs, (va >> 32UL) & 0xFFUL);
projects / mesa.git / blobdiff