r600g: move some code out of draw_vbo into new r600_update_derived_state

[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c

diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 3a6298115ae0ec4be5d0ac52e750b29ff1025f21..2261527cc331ba8e88aa4692794466f2148caa71 100644 (file)
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -35,7 +35,7 @@
 
 static void r600_spi_update(struct r600_pipe_context *rctx);
 
-static int r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
+static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
 {
        static const int prim_conv[] = {
                V_008958_DI_PT_POINTLIST,
@@ -57,9 +57,9 @@ static int r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
        *prim = prim_conv[pprim];
        if (*prim == -1) {
                fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
-               return -1;
+               return false;
        }
-       return 0;
+       return true;
 }
 
 /* common state between evergreen and r600 */
@@ -150,7 +150,7 @@ void r600_delete_state(struct pipe_context *ctx, void *state)
                rctx->states[rstate->id] = NULL;
        }
        for (int i = 0; i < rstate->nregs; i++) {
-               r600_bo_reference(&rstate->regs[i].bo, NULL);
+               pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
        }
        free(rstate);
 }
@@ -181,7 +181,7 @@ void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
        if (rctx->vertex_elements == state)
                rctx->vertex_elements = NULL;
 
-       r600_bo_reference(&v->fetch_shader, NULL);
+       pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
        u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
        FREE(state);
 }
@@ -428,7 +428,7 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
                                        0xFFFFFFFF, NULL, 0);
                r600_pipe_state_add_reg(&rctx->vs_const_buffer,
                                        R_028980_ALU_CONST_CACHE_VS_0,
-                                       offset >> 8, 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READ);
+                                       offset >> 8, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
                r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
 
                rstate = &rctx->vs_const_buffer_resource[index];
@@ -456,7 +456,7 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
                                        0xFFFFFFFF, NULL, 0);
                r600_pipe_state_add_reg(&rctx->ps_const_buffer,
                                        R_028940_ALU_CONST_CACHE_PS_0,
-                                       offset >> 8, 0xFFFFFFFF, rbuffer->bo, RADEON_USAGE_READ);
+                                       offset >> 8, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
                r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
 
                rstate = &rctx->ps_const_buffer_resource[index];
@@ -552,6 +552,36 @@ static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shade
        return 0;
 }
 
+static void r600_update_derived_state(struct r600_pipe_context *rctx)
+{
+       if (!rctx->blit) {
+               if (rctx->have_depth_fb || rctx->have_depth_texture)
+                       r600_flush_depth_textures(rctx);
+       }
+
+       if (rctx->chip_class < EVERGREEN) {
+               r600_update_sampler_states(rctx);
+       }
+
+       if (rctx->vs_shader->shader.clamp_color != rctx->clamp_vertex_color) {
+               r600_shader_rebuild(&rctx->context, rctx->vs_shader);
+       }
+
+       if ((rctx->ps_shader->shader.clamp_color != rctx->clamp_fragment_color) ||
+           ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
+            (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
+               r600_shader_rebuild(&rctx->context, rctx->ps_shader);
+       }
+
+       if (rctx->spi_dirty) {
+               r600_spi_update(rctx);
+       }
+
+       if (rctx->alpha_ref_dirty) {
+               r600_update_alpha_ref(rctx);
+       }
+}
+
 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 {
        struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
@@ -560,13 +590,12 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
        struct r600_drawl draw;
        unsigned prim, mask;
 
-       if (!rctx->blit) {
-               if (rctx->have_depth_fb || rctx->have_depth_texture)
-                       r600_flush_depth_textures(rctx);
+       if (!info->count ||
+           !r600_conv_pipe_prim(info->mode, &prim)) {
+               return;
        }
 
-       if (rctx->chip_class < EVERGREEN)
-               r600_update_sampler_states(rctx);
+       r600_update_derived_state(rctx);
 
        u_vbuf_draw_begin(rctx->vbuf_mgr, info);
        r600_vertex_buffer_update(rctx);
@@ -601,22 +630,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                draw.info.index_bias = info->start;
        }
 
-       if (r600_conv_pipe_prim(draw.info.mode, &prim))
-               return;
-
-       if (rctx->vs_shader->shader.clamp_color != rctx->clamp_vertex_color)
-               r600_shader_rebuild(ctx, rctx->vs_shader);
-
-       if ((rctx->ps_shader->shader.clamp_color != rctx->clamp_fragment_color) ||
-           ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
-            (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs)))
-               r600_shader_rebuild(ctx, rctx->ps_shader);
-
-       if (rctx->spi_dirty)
-               r600_spi_update(rctx);
-
-       if (rctx->alpha_ref_dirty)
-               r600_update_alpha_ref(rctx);
 
        mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 
@@ -656,14 +669,20 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 
        rdraw.vgt_num_indices = draw.info.count;
        rdraw.vgt_num_instances = draw.info.instance_count;
-       rdraw.vgt_index_type = ((draw.index_size == 4) ? 1 : 0);
-       if (R600_BIG_ENDIAN)
-               rdraw.vgt_index_type |= (draw.index_size >> 1) << 2;
-       rdraw.vgt_draw_initiator = draw.index_size ? 0 : 2;
+
+       rdraw.vgt_index_type = draw.index_size == 4 ? VGT_INDEX_32 : VGT_INDEX_16;
+       if (R600_BIG_ENDIAN) {
+               rdraw.vgt_index_type |= draw.index_size == 4 ? VGT_DMA_SWAP_32_BIT
+                                                            : VGT_DMA_SWAP_16_BIT;
+       }
+
+       rdraw.vgt_draw_initiator = draw.index_size ? V_0287F0_DI_SRC_SEL_DMA
+                                                  : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
+
        rdraw.indices = NULL;
        if (draw.index_buffer) {
                rbuffer = (struct r600_resource*)draw.index_buffer;
-               rdraw.indices = rbuffer->bo;
+               rdraw.indices = rbuffer;
                rdraw.indices_bo_offset = draw.index_buffer_offset;
        }
 
@@ -688,7 +707,7 @@ void _r600_pipe_state_add_reg(struct r600_context *ctx,
                              struct r600_pipe_state *state,
                              u32 offset, u32 value, u32 mask,
                              u32 range_id, u32 block_id,
-                             struct r600_bo *bo,
+                             struct r600_resource *bo,
                              enum radeon_bo_usage usage)
 {
        struct r600_range *range;
@@ -712,7 +731,7 @@ void _r600_pipe_state_add_reg(struct r600_context *ctx,
 
 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
                                     u32 offset, u32 value, u32 mask,
-                                    struct r600_bo *bo,
+                                    struct r600_resource *bo,
                                     enum radeon_bo_usage usage)
 {
        if (bo) assert(usage);