* Authors: Dave Airlie <airlied@redhat.com>
* Jerome Glisse <jglisse@redhat.com>
*/
-#include <util/u_memory.h>
-#include <util/u_format.h>
-#include <pipebuffer/pb_buffer.h>
+#include "util/u_memory.h"
+#include "util/u_format.h"
+#include "pipebuffer/pb_buffer.h"
#include "pipe/p_shader_tokens.h"
+#include "tgsi/tgsi_parse.h"
#include "r600_formats.h"
#include "r600_pipe.h"
#include "r600d.h"
static void r600_spi_update(struct r600_pipe_context *rctx);
-static int r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
+static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
{
static const int prim_conv[] = {
V_008958_DI_PT_POINTLIST,
*prim = prim_conv[pprim];
if (*prim == -1) {
fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
- return -1;
+ return false;
}
- return 0;
+ return true;
}
/* common state between evergreen and r600 */
if (state == NULL)
return;
+ rctx->clamp_vertex_color = rs->clamp_vertex_color;
+ rctx->clamp_fragment_color = rs->clamp_fragment_color;
rctx->flatshade = rs->flatshade;
rctx->sprite_coord_enable = rs->sprite_coord_enable;
rctx->rasterizer = rs;
rctx->states[rs->rstate.id] = &rs->rstate;
r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_polygon_offset_update(rctx);
} else {
r600_polygon_offset_update(rctx);
}
if (rctx->ps_shader && rctx->vs_shader)
- r600_spi_update(rctx);
+ rctx->spi_dirty = true;
}
void r600_delete_rs_state(struct pipe_context *ctx, void *state)
rctx->states[rstate->id] = NULL;
}
for (int i = 0; i < rstate->nregs; i++) {
- r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
+ pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
}
free(rstate);
}
rctx->vertex_elements = v;
if (v) {
- u_vbuf_mgr_bind_vertex_elements(rctx->vbuf_mgr, state,
+ u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
v->vmgr_elements);
rctx->states[v->rstate.id] = &v->rstate;
if (rctx->vertex_elements == state)
rctx->vertex_elements = NULL;
- r600_bo_reference(rctx->radeon, &v->fetch_shader, NULL);
- u_vbuf_mgr_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
+ pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
+ u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
FREE(state);
}
/* Zero states. */
for (i = 0; i < count; i++) {
if (!buffers[i].buffer) {
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
} else {
r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
}
}
for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
} else {
r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
}
}
- u_vbuf_mgr_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
+ u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
}
void *r600_create_vertex_elements(struct pipe_context *ctx,
v->count = count;
v->vmgr_elements =
- u_vbuf_mgr_create_vertex_elements(rctx->vbuf_mgr, count,
+ u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
elements, v->elements);
if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
int r;
- r = r600_pipe_shader_create(ctx, shader, state->tokens);
+ shader->tokens = tgsi_dup_tokens(state->tokens);
+
+ r = r600_pipe_shader_create(ctx, shader);
if (r) {
return NULL;
}
r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
}
if (rctx->ps_shader && rctx->vs_shader) {
- r600_spi_update(rctx);
+ rctx->spi_dirty = true;
r600_adjust_gprs(rctx);
}
}
r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_shader->rstate);
}
if (rctx->ps_shader && rctx->vs_shader) {
- r600_spi_update(rctx);
+ rctx->spi_dirty = true;
r600_adjust_gprs(rctx);
}
}
rctx->ps_shader = NULL;
}
+ free(shader->tokens);
r600_pipe_shader_destroy(ctx, shader);
free(shader);
}
rctx->vs_shader = NULL;
}
+ free(shader->tokens);
r600_pipe_shader_destroy(ctx, shader);
free(shader);
}
rstate.nregs = 0;
if (rctx->export_16bpc)
alpha_ref &= ~0x1FFF;
- r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL, 0);
r600_context_pipe_state_set(&rctx->ctx, &rstate);
rctx->alpha_ref_dirty = false;
rstate->nregs = 0;
rstate->id = R600_PIPE_STATE_SPI;
for (i = 0; i < 32; i++) {
- r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, 0, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, 0, 0xFFFFFFFF, NULL, 0);
}
}
for (i = 0; i < rshader->ninput; i++) {
if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
rshader->input[i].name == TGSI_SEMANTIC_FACE)
- if (rctx->family >= CHIP_CEDAR)
+ if (rctx->chip_class >= EVERGREEN)
continue;
else
sid=0;
tmp |= S_028644_PT_SPRITE_TEX(1);
}
- if (rctx->family < CHIP_CEDAR) {
+ if (rctx->chip_class < EVERGREEN) {
if (rshader->input[i].centroid)
tmp |= S_028644_SEL_CENTROID(1);
r600_pipe_state_mod_reg(rstate, tmp);
}
+ rctx->spi_dirty = false;
r600_context_pipe_state_set(&rctx->ctx, rstate);
}
struct pipe_resource *buffer)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- struct r600_resource_buffer *rbuffer = r600_buffer(buffer);
+ struct r600_resource *rbuffer = r600_resource(buffer);
struct r600_pipe_resource_state *rstate;
uint32_t offset;
}
r600_upload_const_buffer(rctx, &rbuffer, &offset);
- offset += r600_bo_offset(rbuffer->r.bo);
switch (shader) {
case PIPE_SHADER_VERTEX:
r600_pipe_state_add_reg(&rctx->vs_const_buffer,
R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
ALIGN_DIVUP(buffer->width0 >> 4, 16),
- 0xFFFFFFFF, NULL);
+ 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(&rctx->vs_const_buffer,
R_028980_ALU_CONST_CACHE_VS_0,
- offset >> 8, 0xFFFFFFFF, rbuffer->r.bo);
+ offset >> 8, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
rstate = &rctx->vs_const_buffer_resource[index];
if (!rstate->id) {
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_pipe_init_buffer_resource(rctx, rstate);
} else {
r600_pipe_init_buffer_resource(rctx, rstate);
}
}
- if (rctx->family >= CHIP_CEDAR) {
- evergreen_pipe_mod_buffer_resource(rstate, &rbuffer->r, offset, 16);
+ if (rctx->chip_class >= EVERGREEN) {
+ evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
} else {
- r600_pipe_mod_buffer_resource(rstate, &rbuffer->r, offset, 16);
+ r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
}
break;
r600_pipe_state_add_reg(&rctx->ps_const_buffer,
R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
ALIGN_DIVUP(buffer->width0 >> 4, 16),
- 0xFFFFFFFF, NULL);
+ 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(&rctx->ps_const_buffer,
R_028940_ALU_CONST_CACHE_PS_0,
- offset >> 8, 0xFFFFFFFF, rbuffer->r.bo);
+ offset >> 8, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
rstate = &rctx->ps_const_buffer_resource[index];
if (!rstate->id) {
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_pipe_init_buffer_resource(rctx, rstate);
} else {
r600_pipe_init_buffer_resource(rctx, rstate);
}
}
- if (rctx->family >= CHIP_CEDAR) {
- evergreen_pipe_mod_buffer_resource(rstate, &rbuffer->r, offset, 16);
+ if (rctx->chip_class >= EVERGREEN) {
+ evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
} else {
- r600_pipe_mod_buffer_resource(rstate, &rbuffer->r, offset, 16);
+ r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
r600_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
}
break;
return;
}
- if (buffer != &rbuffer->r.b.b.b)
+ if (buffer != &rbuffer->b.b.b)
pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
}
/* one resource per vertex elements */
unsigned vbuffer_index;
vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
- vertex_buffer = &rctx->vbuf_mgr->vertex_buffer[vbuffer_index];
- rbuffer = (struct r600_resource*)rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
+ vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
+ rbuffer = (struct r600_resource*)vertex_buffer->buffer;
offset = rctx->vertex_elements->vbuffer_offset[i];
} else {
/* bind vertex buffer once */
- vertex_buffer = &rctx->vbuf_mgr->vertex_buffer[i];
- rbuffer = (struct r600_resource*)rctx->vbuf_mgr->real_vertex_buffer[i];
+ vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
+ rbuffer = (struct r600_resource*)vertex_buffer->buffer;
offset = 0;
}
if (vertex_buffer == NULL || rbuffer == NULL)
continue;
- offset += vertex_buffer->buffer_offset + r600_bo_offset(rbuffer->bo);
+ offset += vertex_buffer->buffer_offset;
if (!rstate->id) {
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_pipe_init_buffer_resource(rctx, rstate);
} else {
r600_pipe_init_buffer_resource(rctx, rstate);
}
}
- if (rctx->family >= CHIP_CEDAR) {
- evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride);
+ if (rctx->chip_class >= EVERGREEN) {
+ evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
} else {
- r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride);
+ r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
}
}
}
-void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
+static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- struct r600_resource *rbuffer;
- u32 vgt_dma_index_type, vgt_dma_swap_mode, vgt_draw_initiator, mask;
- struct r600_draw rdraw;
- struct r600_drawl draw = {};
- unsigned prim;
+ int r;
+ r600_pipe_shader_destroy(ctx, shader);
+ r = r600_pipe_shader_create(ctx, shader);
+ if (r) {
+ return r;
+ }
+ r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
+
+ return 0;
+}
+
+static void r600_update_derived_state(struct r600_pipe_context *rctx)
+{
if (!rctx->blit) {
if (rctx->have_depth_fb || rctx->have_depth_texture)
r600_flush_depth_textures(rctx);
}
- u_vbuf_mgr_draw_begin(rctx->vbuf_mgr, info);
+
+ if (rctx->chip_class < EVERGREEN) {
+ r600_update_sampler_states(rctx);
+ }
+
+ if (rctx->vs_shader->shader.clamp_color != rctx->clamp_vertex_color) {
+ r600_shader_rebuild(&rctx->context, rctx->vs_shader);
+ }
+
+ if ((rctx->ps_shader->shader.clamp_color != rctx->clamp_fragment_color) ||
+ ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
+ (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
+ r600_shader_rebuild(&rctx->context, rctx->ps_shader);
+ }
+
+ if (rctx->spi_dirty) {
+ r600_spi_update(rctx);
+ }
+
+ if (rctx->alpha_ref_dirty) {
+ r600_update_alpha_ref(rctx);
+ }
+}
+
+void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_resource *rbuffer;
+ struct r600_draw rdraw;
+ struct r600_drawl draw;
+ unsigned prim, mask;
+
+ if (!info->count ||
+ !r600_conv_pipe_prim(info->mode, &prim)) {
+ return;
+ }
+
+ r600_update_derived_state(rctx);
+
+ u_vbuf_draw_begin(rctx->vbuf_mgr, info);
r600_vertex_buffer_update(rctx);
draw.info = *info;
+ if (draw.info.max_index != ~0) {
+ draw.info.min_index += info->index_bias;
+ draw.info.max_index += info->index_bias;
+ }
+
draw.ctx = ctx;
+ draw.index_buffer = NULL;
if (info->indexed && rctx->index_buffer.buffer) {
draw.info.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
r600_upload_index_buffer(rctx, &draw);
}
} else {
+ draw.index_size = 0;
+ draw.index_buffer_offset = 0;
draw.info.index_bias = info->start;
}
- vgt_dma_swap_mode = 0;
- switch (draw.index_size) {
- case 2:
- vgt_draw_initiator = 0;
- vgt_dma_index_type = 0;
- if (R600_BIG_ENDIAN) {
- vgt_dma_swap_mode = ENDIAN_8IN16;
- }
- break;
- case 4:
- vgt_draw_initiator = 0;
- vgt_dma_index_type = 1;
- if (R600_BIG_ENDIAN) {
- vgt_dma_swap_mode = ENDIAN_8IN32;
- }
- break;
- case 0:
- vgt_draw_initiator = 2;
- vgt_dma_index_type = 0;
- break;
- default:
- R600_ERR("unsupported index size %d\n", draw.index_size);
- return;
- }
- if (r600_conv_pipe_prim(draw.info.mode, &prim))
- return;
- if (unlikely(rctx->ps_shader == NULL)) {
- R600_ERR("missing vertex shader\n");
- return;
- }
- if (unlikely(rctx->vs_shader == NULL)) {
- R600_ERR("missing vertex shader\n");
- return;
- }
- /* there should be enough input */
- if (rctx->vertex_elements->count < rctx->vs_shader->shader.bc.nresource) {
- R600_ERR("%d resources provided, expecting %d\n",
- rctx->vertex_elements->count, rctx->vs_shader->shader.bc.nresource);
- return;
- }
-
- if (rctx->alpha_ref_dirty)
- r600_update_alpha_ref(rctx);
- mask = 0;
- for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
- mask |= (0xF << (i * 4));
- }
+ mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
rctx->vgt.id = R600_PIPE_STATE_VGT;
rctx->vgt.nregs = 0;
- r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, draw.info.max_index, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, draw.info.min_index, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, draw.info.index_bias, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
- r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, draw.info.start_instance, 0xFFFFFFFF, NULL);
+ r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, draw.info.max_index, 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, draw.info.min_index, 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, draw.info.index_bias, 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, draw.info.restart_index, 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, draw.info.primitive_restart, 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, draw.info.start_instance, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL,
0,
- S_028814_PROVOKING_VTX_LAST(1), NULL);
+ S_028814_PROVOKING_VTX_LAST(1), NULL, 0);
}
r600_pipe_state_mod_reg(&rctx->vgt, draw.info.max_index);
r600_pipe_state_mod_reg(&rctx->vgt, draw.info.min_index);
r600_pipe_state_mod_reg(&rctx->vgt, draw.info.index_bias);
+ r600_pipe_state_mod_reg(&rctx->vgt, draw.info.restart_index);
+ r600_pipe_state_mod_reg(&rctx->vgt, draw.info.primitive_restart);
r600_pipe_state_mod_reg(&rctx->vgt, 0);
r600_pipe_state_mod_reg(&rctx->vgt, draw.info.start_instance);
if (draw.info.mode == PIPE_PRIM_QUADS || draw.info.mode == PIPE_PRIM_QUAD_STRIP || draw.info.mode == PIPE_PRIM_POLYGON) {
rdraw.vgt_num_indices = draw.info.count;
rdraw.vgt_num_instances = draw.info.instance_count;
- rdraw.vgt_index_type = vgt_dma_index_type | (vgt_dma_swap_mode << 2);
- rdraw.vgt_draw_initiator = vgt_draw_initiator;
+
+ rdraw.vgt_index_type = draw.index_size == 4 ? VGT_INDEX_32 : VGT_INDEX_16;
+ if (R600_BIG_ENDIAN) {
+ rdraw.vgt_index_type |= draw.index_size == 4 ? VGT_DMA_SWAP_32_BIT
+ : VGT_DMA_SWAP_16_BIT;
+ }
+
+ rdraw.vgt_draw_initiator = draw.index_size ? V_0287F0_DI_SRC_SEL_DMA
+ : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
+
rdraw.indices = NULL;
if (draw.index_buffer) {
rbuffer = (struct r600_resource*)draw.index_buffer;
- rdraw.indices = rbuffer->bo;
+ rdraw.indices = rbuffer;
rdraw.indices_bo_offset = draw.index_buffer_offset;
}
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_context_draw(&rctx->ctx, &rdraw);
} else {
r600_context_draw(&rctx->ctx, &rdraw);
pipe_resource_reference(&draw.index_buffer, NULL);
- u_vbuf_mgr_draw_end(rctx->vbuf_mgr);
+ u_vbuf_draw_end(rctx->vbuf_mgr);
}
void _r600_pipe_state_add_reg(struct r600_context *ctx,
struct r600_pipe_state *state,
u32 offset, u32 value, u32 mask,
u32 range_id, u32 block_id,
- struct r600_bo *bo)
+ struct r600_resource *bo,
+ enum radeon_bo_usage usage)
{
struct r600_range *range;
struct r600_block *block;
+ if (bo) assert(usage);
+
range = &ctx->range[range_id];
block = range->blocks[block_id];
state->regs[state->nregs].block = block;
state->regs[state->nregs].value = value;
state->regs[state->nregs].mask = mask;
state->regs[state->nregs].bo = bo;
+ state->regs[state->nregs].bo_usage = usage;
state->nregs++;
assert(state->nregs < R600_BLOCK_MAX_REG);
void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
u32 offset, u32 value, u32 mask,
- struct r600_bo *bo)
+ struct r600_resource *bo,
+ enum radeon_bo_usage usage)
{
+ if (bo) assert(usage);
+
state->regs[state->nregs].id = offset;
state->regs[state->nregs].block = NULL;
state->regs[state->nregs].value = value;
state->regs[state->nregs].mask = mask;
state->regs[state->nregs].bo = bo;
+ state->regs[state->nregs].bo_usage = usage;
state->nregs++;
assert(state->nregs < R600_BLOCK_MAX_REG);
projects / mesa.git / blobdiff