#include "util/u_upload_mgr.h"
#include "util/u_math.h"
#include "tgsi/tgsi_parse.h"
+#include "tgsi/tgsi_scan.h"
+#include "tgsi/tgsi_ureg.h"
void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
{
FREE(cb->buf);
}
+void r600_add_atom(struct r600_context *rctx,
+ struct r600_atom *atom,
+ unsigned id)
+{
+ assert(id < R600_NUM_ATOMS);
+ assert(rctx->atoms[id] == NULL);
+ rctx->atoms[id] = atom;
+ atom->id = id;
+}
+
void r600_init_atom(struct r600_context *rctx,
struct r600_atom *atom,
unsigned id,
void (*emit)(struct r600_context *ctx, struct r600_atom *state),
unsigned num_dw)
{
- assert(id < R600_NUM_ATOMS);
- assert(rctx->atoms[id] == NULL);
- rctx->atoms[id] = atom;
atom->emit = (void*)emit;
atom->num_dw = num_dw;
- atom->dirty = false;
+ r600_add_atom(rctx, atom, id);
}
void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
{
- r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
+ r600_emit_command_buffer(rctx->b.gfx.cs, ((struct r600_cso_state*)atom)->cb);
}
void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
unsigned alpha_ref = a->sx_alpha_ref;
alpha_ref &= ~0x1FFF;
}
- r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
+ radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
a->sx_alpha_test_control |
S_028410_ALPHA_TEST_BYPASS(a->bypass));
- r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
+ radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
}
static void r600_texture_barrier(struct pipe_context *ctx)
static unsigned r600_conv_pipe_prim(unsigned prim)
{
static const unsigned prim_conv[] = {
- V_008958_DI_PT_POINTLIST,
- V_008958_DI_PT_LINELIST,
- V_008958_DI_PT_LINELOOP,
- V_008958_DI_PT_LINESTRIP,
- V_008958_DI_PT_TRILIST,
- V_008958_DI_PT_TRISTRIP,
- V_008958_DI_PT_TRIFAN,
- V_008958_DI_PT_QUADLIST,
- V_008958_DI_PT_QUADSTRIP,
- V_008958_DI_PT_POLYGON,
- V_008958_DI_PT_LINELIST_ADJ,
- V_008958_DI_PT_LINESTRIP_ADJ,
- V_008958_DI_PT_TRILIST_ADJ,
- V_008958_DI_PT_TRISTRIP_ADJ,
- V_008958_DI_PT_RECTLIST
+ [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
+ [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
+ [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
+ [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
+ [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
+ [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
+ [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
+ [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
+ [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
+ [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
+ [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
+ [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
+ [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
+ [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
+ [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
};
+ assert(prim < Elements(prim_conv));
return prim_conv[prim];
}
+unsigned r600_conv_prim_to_gs_out(unsigned mode)
+{
+ static const int prim_conv[] = {
+ [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
+ [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
+ [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
+ };
+ assert(mode < Elements(prim_conv));
+
+ return prim_conv[mode];
+}
+
/* common state between evergreen and r600 */
static void r600_bind_blend_state_internal(struct r600_context *rctx,
rctx->dual_src_blend = blend->dual_src_blend;
if (!blend_disable) {
- r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
+ r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
color_control = blend->cb_color_control;
} else {
/* Blending is disabled. */
- r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
+ r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
color_control = blend->cb_color_control_no_blend;
}
update_cb = true;
}
if (update_cb) {
- rctx->cb_misc_state.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
}
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_blend_state *blend = (struct r600_blend_state *)state;
- if (blend == NULL)
+ if (!blend) {
+ r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
return;
+ }
r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
}
struct r600_context *rctx = (struct r600_context *)ctx;
rctx->blend_color.state = *state;
- rctx->blend_color.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
}
void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
struct pipe_blend_color *state = &rctx->blend_color.state;
- r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
+ radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
- r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
- r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
+ radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
+ radeon_set_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
+ if (a->last_draw_was_indirect) {
+ a->last_draw_was_indirect = false;
+ radeon_set_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
+ }
}
static void r600_set_clip_state(struct pipe_context *ctx,
const struct pipe_clip_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct pipe_constant_buffer cb;
rctx->clip_state.state = *state;
- rctx->clip_state.atom.dirty = true;
-
- cb.buffer = NULL;
- cb.user_buffer = state->ucp;
- cb.buffer_offset = 0;
- cb.buffer_size = 4*4*8;
- ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
- pipe_resource_reference(&cb.buffer, NULL);
+ r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
+ rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
}
static void r600_set_stencil_ref(struct pipe_context *ctx,
struct r600_context *rctx = (struct r600_context *)ctx;
rctx->stencil_ref.state = *state;
- rctx->stencil_ref.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
}
void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
- r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
+ radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
S_028430_STENCILREF(a->state.ref_value[0]) |
S_028430_STENCILMASK(a->state.valuemask[0]) |
struct r600_dsa_state *dsa = state;
struct r600_stencil_ref ref;
- if (state == NULL) {
- r600_set_cso_state_with_cb(&rctx->dsa_state, NULL, NULL);
+ if (!state) {
+ r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
return;
}
- r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
+ r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
if (rctx->zwritemask != dsa->zwritemask) {
rctx->zwritemask = dsa->zwritemask;
if (rctx->b.chip_class >= EVERGREEN) {
- /* work around some issue when not writting to zbuffer
+ /* work around some issue when not writing to zbuffer
* we are having lockup on evergreen so do not enable
- * hyperz when not writting zbuffer
+ * hyperz when not writing zbuffer
*/
- rctx->db_misc_state.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
}
}
rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
- rctx->alphatest_state.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
}
struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
struct r600_context *rctx = (struct r600_context *)ctx;
- if (state == NULL)
+ if (!state)
return;
rctx->rasterizer = rs;
- r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
+ r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
if (rs->offset_enable &&
(rs->offset_units != rctx->poly_offset_state.offset_units ||
rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
rctx->poly_offset_state.offset_units = rs->offset_units;
rctx->poly_offset_state.offset_scale = rs->offset_scale;
- rctx->poly_offset_state.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
}
/* Update clip_misc_state. */
rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
- rctx->clip_misc_state.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
}
/* Workaround for a missing scissor enable on r600. */
if (rctx->b.chip_class == R600 &&
- rs->scissor_enable != rctx->scissor[0].enable) {
- rctx->scissor[0].enable = rs->scissor_enable;
- rctx->scissor[0].atom.dirty = true;
+ rs->scissor_enable != rctx->scissor.enable) {
+ rctx->scissor.enable = rs->scissor_enable;
+ rctx->scissor.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
+ rctx->scissor.atom.num_dw = R600_MAX_VIEWPORTS * 4;
+ r600_mark_atom_dirty(rctx, &rctx->scissor.atom);
}
/* Re-emit PA_SC_LINE_STIPPLE. */
state->atom.num_dw =
util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
- state->atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &state->atom);
}
}
assert(start == 0); /* XXX fix below */
- if (shader != PIPE_SHADER_VERTEX &&
- shader != PIPE_SHADER_FRAGMENT) {
- return;
+ if (!states) {
+ disable_mask = ~0u;
+ count = 0;
}
for (i = 0; i < count; i++) {
/* change in TA_CNTL_AUX need a pipeline flush */
rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
rctx->seamless_cube_map.enabled = seamless_cube_map;
- rctx->seamless_cube_map.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
}
}
static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
{
+ struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_blend_state *blend = (struct r600_blend_state*)state;
+ if (rctx->blend_state.cso == state) {
+ ctx->bind_blend_state(ctx, NULL);
+ }
+
r600_release_command_buffer(&blend->buffer);
r600_release_command_buffer(&blend->buffer_no_blend);
FREE(blend);
{
struct r600_context *rctx = (struct r600_context *)ctx;
- r600_set_cso_state(&rctx->vertex_fetch_shader, state);
+ r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
}
static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
util_bitcount(rctx->vertex_buffer_state.dirty_mask);
- rctx->vertex_buffer_state.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
}
}
rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
util_bitcount(state->dirty_mask);
- state->atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &state->atom);
}
}
assert(start == 0); /* XXX fix below */
- if (shader == PIPE_SHADER_COMPUTE) {
- evergreen_set_cs_sampler_view(pipe, start, count, views);
- return;
+ if (!views) {
+ disable_mask = ~0u;
+ count = 0;
}
remaining_mask = dst->views.enabled_mask & disable_mask;
dst->views.dirty_mask |= new_mask;
dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
- dst->views.dirty_txq_constants = TRUE;
dst->views.dirty_buffer_constants = TRUE;
r600_sampler_views_dirty(rctx, &dst->views);
const struct pipe_viewport_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_viewport_state *rstate = &rctx->viewport;
int i;
- for (i = start_slot; i < start_slot + num_viewports; i++) {
- rctx->viewport[i].state = state[i - start_slot];
- rctx->viewport[i].atom.dirty = true;
- }
+ for (i = start_slot; i < start_slot + num_viewports; i++)
+ rstate->state[i] = state[i - start_slot];
+ rstate->dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
+ rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 8;
+ r600_mark_atom_dirty(rctx, &rctx->viewport.atom);
}
void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
- struct r600_viewport_state *rstate = (struct r600_viewport_state *)atom;
- struct pipe_viewport_state *state = &rstate->state;
- int offset = rstate->idx * 6 * 4;
-
- r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0 + offset, 6);
- radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
- radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
- radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
- radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
- radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
- radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
+ struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
+ struct r600_viewport_state *rstate = &rctx->viewport;
+ struct pipe_viewport_state *state;
+ uint32_t dirty_mask;
+ unsigned i, offset;
+
+ dirty_mask = rstate->dirty_mask;
+ while (dirty_mask != 0) {
+ i = u_bit_scan(&dirty_mask);
+ offset = i * 6 * 4;
+ radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0 + offset, 6);
+ state = &rstate->state[i];
+ radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
+ radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
+ radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
+ radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
+ radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
+ radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
+ }
+ rstate->dirty_mask = 0;
+ rstate->atom.num_dw = 0;
}
/* Compute the key for the hw shader variant */
-static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
+static inline union r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
struct r600_pipe_shader_selector * sel)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_shader_key key;
+ union r600_shader_key key;
memset(&key, 0, sizeof(key));
- if (sel->type == PIPE_SHADER_FRAGMENT) {
- key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
- key.alpha_to_one = rctx->alpha_to_one &&
- rctx->rasterizer && rctx->rasterizer->multisample_enable &&
- !rctx->framebuffer.cb0_is_integer;
- key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
+ switch (sel->type) {
+ case PIPE_SHADER_VERTEX: {
+ key.vs.as_ls = (rctx->tes_shader != NULL);
+ if (!key.vs.as_ls)
+ key.vs.as_es = (rctx->gs_shader != NULL);
+
+ if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
+ key.vs.as_gs_a = true;
+ key.vs.prim_id_out = rctx->ps_shader->current->shader.input[rctx->ps_shader->current->shader.ps_prim_id_input].spi_sid;
+ }
+ break;
+ }
+ case PIPE_SHADER_GEOMETRY:
+ break;
+ case PIPE_SHADER_FRAGMENT: {
+ key.ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
+ key.ps.alpha_to_one = rctx->alpha_to_one &&
+ rctx->rasterizer && rctx->rasterizer->multisample_enable &&
+ !rctx->framebuffer.cb0_is_integer;
+ key.ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
/* Dual-source blending only makes sense with nr_cbufs == 1. */
- if (key.nr_cbufs == 1 && rctx->dual_src_blend)
- key.nr_cbufs = 2;
- } else if (sel->type == PIPE_SHADER_VERTEX) {
- key.vs_as_es = (rctx->gs_shader != NULL);
+ if (key.ps.nr_cbufs == 1 && rctx->dual_src_blend)
+ key.ps.nr_cbufs = 2;
+ break;
+ }
+ case PIPE_SHADER_TESS_EVAL:
+ key.tes.as_es = (rctx->gs_shader != NULL);
+ break;
+ case PIPE_SHADER_TESS_CTRL:
+ key.tcs.prim_mode = rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
+ break;
+ default:
+ assert(0);
}
+
return key;
}
struct r600_pipe_shader_selector* sel,
bool *dirty)
{
- struct r600_shader_key key;
+ union r600_shader_key key;
struct r600_pipe_shader * shader = NULL;
int r;
unsigned pipe_shader_type)
{
struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
+ int i;
sel->type = pipe_shader_type;
sel->tokens = tgsi_dup_tokens(state->tokens);
sel->so = state->stream_output;
+ tgsi_scan_shader(state->tokens, &sel->info);
+
+ switch (pipe_shader_type) {
+ case PIPE_SHADER_GEOMETRY:
+ sel->gs_output_prim =
+ sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
+ sel->gs_max_out_vertices =
+ sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
+ sel->gs_num_invocations =
+ sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
+ break;
+ case PIPE_SHADER_VERTEX:
+ case PIPE_SHADER_TESS_CTRL:
+ sel->lds_patch_outputs_written_mask = 0;
+ sel->lds_outputs_written_mask = 0;
+
+ for (i = 0; i < sel->info.num_outputs; i++) {
+ unsigned name = sel->info.output_semantic_name[i];
+ unsigned index = sel->info.output_semantic_index[i];
+
+ switch (name) {
+ case TGSI_SEMANTIC_TESSINNER:
+ case TGSI_SEMANTIC_TESSOUTER:
+ case TGSI_SEMANTIC_PATCH:
+ sel->lds_patch_outputs_written_mask |=
+ 1llu << r600_get_lds_unique_index(name, index);
+ break;
+ default:
+ sel->lds_outputs_written_mask |=
+ 1llu << r600_get_lds_unique_index(name, index);
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
return sel;
}
return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
}
+static void *r600_create_tcs_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
+}
+
+static void *r600_create_tes_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
+}
+
static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
}
+static void r600_bind_tcs_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ rctx->tcs_shader = (struct r600_pipe_shader_selector *)state;
+}
+
+static void r600_bind_tes_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ rctx->tes_shader = (struct r600_pipe_shader_selector *)state;
+
+ if (!state)
+ return;
+ rctx->b.streamout.stride_in_dw = rctx->tes_shader->so.stride;
+}
+
static void r600_delete_shader_selector(struct pipe_context *ctx,
struct r600_pipe_shader_selector *sel)
{
r600_delete_shader_selector(ctx, sel);
}
+static void r600_delete_tcs_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
+
+ if (rctx->tcs_shader == sel) {
+ rctx->tcs_shader = NULL;
+ }
+
+ r600_delete_shader_selector(ctx, sel);
+}
+
+static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
+
+ if (rctx->tes_shader == sel) {
+ rctx->tes_shader = NULL;
+ }
+
+ r600_delete_shader_selector(ctx, sel);
+}
void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
{
rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
: util_bitcount(state->dirty_mask)*19;
- state->atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &state->atom);
}
}
return;
rctx->sample_mask.sample_mask = sample_mask;
- rctx->sample_mask.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
+}
+
+static void r600_update_driver_const_buffers(struct r600_context *rctx)
+{
+ int sh, size;;
+ void *ptr;
+ struct pipe_constant_buffer cb;
+ for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
+ struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
+ if (!info->vs_ucp_dirty &&
+ !info->texture_const_dirty &&
+ !info->ps_sample_pos_dirty)
+ continue;
+
+ ptr = info->constants;
+ size = info->alloc_size;
+ if (info->vs_ucp_dirty) {
+ assert(sh == PIPE_SHADER_VERTEX);
+ if (!size) {
+ ptr = rctx->clip_state.state.ucp;
+ size = R600_UCP_SIZE;
+ } else {
+ memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
+ }
+ info->vs_ucp_dirty = false;
+ }
+
+ if (info->ps_sample_pos_dirty) {
+ assert(sh == PIPE_SHADER_FRAGMENT);
+ if (!size) {
+ ptr = rctx->sample_positions;
+ size = R600_UCP_SIZE;
+ } else {
+ memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
+ }
+ info->ps_sample_pos_dirty = false;
+ }
+
+ if (info->texture_const_dirty) {
+ assert (ptr);
+ assert (size);
+ if (sh == PIPE_SHADER_VERTEX)
+ memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
+ if (sh == PIPE_SHADER_FRAGMENT)
+ memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
+ }
+ info->texture_const_dirty = false;
+
+ cb.buffer = NULL;
+ cb.user_buffer = ptr;
+ cb.buffer_offset = 0;
+ cb.buffer_size = size;
+ rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, &cb);
+ pipe_resource_reference(&cb.buffer, NULL);
+ }
}
+static void *r600_alloc_buf_consts(struct r600_context *rctx, int shader_type,
+ int array_size, uint32_t *base_offset)
+{
+ struct r600_shader_driver_constants_info *info = &rctx->driver_consts[shader_type];
+ if (array_size + R600_UCP_SIZE > info->alloc_size) {
+ info->constants = realloc(info->constants, array_size + R600_UCP_SIZE);
+ info->alloc_size = array_size + R600_UCP_SIZE;
+ }
+ memset(info->constants + (R600_UCP_SIZE / 4), 0, array_size);
+ info->texture_const_dirty = true;
+ *base_offset = R600_UCP_SIZE;
+ return info->constants;
+}
/*
* On r600/700 hw we don't have vertex fetch swizzle, though TBO
* doesn't require full swizzles it does need masking and setting alpha
* then in the shader, we AND the 4 components with 0xffffffff or 0,
* then OR the alpha with the value given here.
* We use a 6th constant to store the txq buffer size in
+ * we use 7th slot for number of cube layers in a cube map array.
*/
static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
{
struct r600_textures_info *samplers = &rctx->samplers[shader_type];
int bits;
uint32_t array_size;
- struct pipe_constant_buffer cb;
int i, j;
-
+ uint32_t *constants;
+ uint32_t base_offset;
if (!samplers->views.dirty_buffer_constants)
return;
bits = util_last_bit(samplers->views.enabled_mask);
array_size = bits * 8 * sizeof(uint32_t) * 4;
- samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
- memset(samplers->buffer_constants, 0, array_size);
+
+ constants = r600_alloc_buf_consts(rctx, shader_type, array_size, &base_offset);
+
for (i = 0; i < bits; i++) {
if (samplers->views.enabled_mask & (1 << i)) {
- int offset = i * 8;
+ int offset = (base_offset / 4) + i * 8;
const struct util_format_description *desc;
desc = util_format_description(samplers->views.views[i]->base.format);
for (j = 0; j < 4; j++)
if (j < desc->nr_channels)
- samplers->buffer_constants[offset+j] = 0xffffffff;
+ constants[offset+j] = 0xffffffff;
else
- samplers->buffer_constants[offset+j] = 0x0;
+ constants[offset+j] = 0x0;
if (desc->nr_channels < 4) {
if (desc->channel[0].pure_integer)
- samplers->buffer_constants[offset+4] = 1;
+ constants[offset+4] = 1;
else
- samplers->buffer_constants[offset+4] = 0x3f800000;
+ constants[offset+4] = fui(1.0);
} else
- samplers->buffer_constants[offset + 4] = 0;
+ constants[offset + 4] = 0;
- samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
+ constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
+ constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
}
}
- cb.buffer = NULL;
- cb.user_buffer = samplers->buffer_constants;
- cb.buffer_offset = 0;
- cb.buffer_size = array_size;
- rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
- pipe_resource_reference(&cb.buffer, NULL);
}
-/* On evergreen we only need to store the buffer size for TXQ */
+/* On evergreen we store two values
+ * 1. buffer size for TXQ
+ * 2. number of cube layers in a cube map array.
+ */
static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
{
struct r600_textures_info *samplers = &rctx->samplers[shader_type];
int bits;
uint32_t array_size;
- struct pipe_constant_buffer cb;
int i;
-
+ uint32_t *constants;
+ uint32_t base_offset;
if (!samplers->views.dirty_buffer_constants)
return;
samplers->views.dirty_buffer_constants = FALSE;
bits = util_last_bit(samplers->views.enabled_mask);
- array_size = bits * sizeof(uint32_t) * 4;
- samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
- memset(samplers->buffer_constants, 0, array_size);
- for (i = 0; i < bits; i++)
- if (samplers->views.enabled_mask & (1 << i))
- samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
+ array_size = bits * 2 * sizeof(uint32_t) * 4;
- cb.buffer = NULL;
- cb.user_buffer = samplers->buffer_constants;
- cb.buffer_offset = 0;
- cb.buffer_size = array_size;
- rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
- pipe_resource_reference(&cb.buffer, NULL);
+ constants = r600_alloc_buf_consts(rctx, shader_type, array_size,
+ &base_offset);
+
+ for (i = 0; i < bits; i++) {
+ if (samplers->views.enabled_mask & (1 << i)) {
+ uint32_t offset = (base_offset / 4) + i * 2;
+ constants[offset] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
+ constants[offset + 1] = samplers->views.views[i]->base.texture->array_size / 6;
+ }
+ }
}
-static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
+/* set sample xy locations as array of fragment shader constants */
+void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
{
- struct r600_textures_info *samplers = &rctx->samplers[shader_type];
- int bits;
- uint32_t array_size;
- struct pipe_constant_buffer cb;
int i;
+ struct pipe_context *ctx = &rctx->b.b;
- if (!samplers->views.dirty_txq_constants)
- return;
-
- samplers->views.dirty_txq_constants = FALSE;
+ assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE);
+ assert(rctx->framebuffer.nr_samples <= Elements(rctx->sample_positions)/4);
- bits = util_last_bit(samplers->views.enabled_mask);
- array_size = bits * sizeof(uint32_t) * 4;
- samplers->txq_constants = realloc(samplers->txq_constants, array_size);
- memset(samplers->txq_constants, 0, array_size);
- for (i = 0; i < bits; i++)
- if (samplers->views.enabled_mask & (1 << i))
- samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
+ memset(rctx->sample_positions, 0, 4 * 4 * 16);
+ for (i = 0; i < rctx->framebuffer.nr_samples; i++) {
+ ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]);
+ /* Also fill in center-zeroed positions used for interpolateAtSample */
+ rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f;
+ rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f;
+ }
- cb.buffer = NULL;
- cb.user_buffer = samplers->txq_constants;
- cb.buffer_offset = 0;
- cb.buffer_size = array_size;
- rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_TXQ_CONST_BUFFER, &cb);
- pipe_resource_reference(&cb.buffer, NULL);
+ rctx->driver_consts[PIPE_SHADER_FRAGMENT].ps_sample_pos_dirty = true;
}
static void update_shader_atom(struct pipe_context *ctx,
struct r600_shader_state *state,
struct r600_pipe_shader *shader)
{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
state->shader = shader;
if (shader) {
state->atom.num_dw = shader->command_buffer.num_dw;
- state->atom.dirty = true;
r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
} else {
state->atom.num_dw = 0;
- state->atom.dirty = false;
}
+ r600_mark_atom_dirty(rctx, &state->atom);
}
static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
{
if (rctx->shader_stages.geom_enable != enable) {
rctx->shader_stages.geom_enable = enable;
- rctx->shader_stages.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
}
if (rctx->gs_rings.enable != enable) {
rctx->gs_rings.enable = enable;
- rctx->gs_rings.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
if (enable && !rctx->gs_rings.esgs_ring.buffer) {
unsigned size = 0x1C000;
if (enable) {
r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.esgs_ring);
- r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
- R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
+ if (rctx->tes_shader) {
+ r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
+ R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
+ } else {
+ r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
+ R600_GS_RING_CONST_BUFFER, &rctx->gs_rings.gsvs_ring);
+ }
} else {
r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
R600_GS_RING_CONST_BUFFER, NULL);
r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
R600_GS_RING_CONST_BUFFER, NULL);
+ r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
+ R600_GS_RING_CONST_BUFFER, NULL);
}
}
}
+static void r600_update_clip_state(struct r600_context *rctx,
+ struct r600_pipe_shader *current)
+{
+ if (current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
+ current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
+ current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable ||
+ current->shader.vs_out_viewport != rctx->clip_misc_state.vs_out_viewport) {
+ rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
+ rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
+ rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
+ rctx->clip_misc_state.vs_out_viewport = current->shader.vs_out_viewport;
+ r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
+ }
+}
+
+static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
+{
+ struct ureg_src const0, const1;
+ struct ureg_dst tessouter, tessinner;
+ struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
+
+ if (!ureg)
+ return; /* if we get here, we're screwed */
+
+ assert(!rctx->fixed_func_tcs_shader);
+
+ ureg_DECL_constant2D(ureg, 0, 3, R600_LDS_INFO_CONST_BUFFER);
+ const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 2),
+ R600_LDS_INFO_CONST_BUFFER);
+ const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 3),
+ R600_LDS_INFO_CONST_BUFFER);
+
+ tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
+ tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
+
+ ureg_MOV(ureg, tessouter, const0);
+ ureg_MOV(ureg, tessinner, const1);
+ ureg_END(ureg);
+
+ rctx->fixed_func_tcs_shader =
+ ureg_create_shader_and_destroy(ureg, &rctx->b.b);
+}
+
+#define SELECT_SHADER_OR_FAIL(x) do { \
+ r600_shader_select(ctx, rctx->x##_shader, &x##_dirty); \
+ if (unlikely(!rctx->x##_shader->current)) \
+ return false; \
+ } while(0)
+
+#define UPDATE_SHADER(hw, sw) do { \
+ if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
+ update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
+ } while(0)
+
+#define UPDATE_SHADER_CLIP(hw, sw) do { \
+ if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
+ update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
+ clip_so_current = rctx->sw##_shader->current; \
+ } \
+ } while(0)
+
+#define UPDATE_SHADER_GS(hw, hw2, sw) do { \
+ if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
+ update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
+ update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
+ clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
+ } \
+ } while(0)
+
+#define SET_NULL_SHADER(hw) do { \
+ if (rctx->hw_shader_stages[(hw)].shader) \
+ update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
+ } while (0)
+
static bool r600_update_derived_state(struct r600_context *rctx)
{
struct pipe_context * ctx = (struct pipe_context*)rctx;
bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
+ bool tcs_dirty = false, tes_dirty = false, fixed_func_tcs_dirty = false;
bool blend_disable;
+ bool need_buf_const;
+ struct r600_pipe_shader *clip_so_current = NULL;
if (!rctx->blitter->running) {
unsigned i;
}
}
+ SELECT_SHADER_OR_FAIL(ps);
+
+ r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
+
update_gs_block_state(rctx, rctx->gs_shader != NULL);
- if (rctx->gs_shader) {
- r600_shader_select(ctx, rctx->gs_shader, &gs_dirty);
- if (unlikely(!rctx->gs_shader->current))
- return false;
+ if (rctx->gs_shader)
+ SELECT_SHADER_OR_FAIL(gs);
+
+ /* Hull Shader */
+ if (rctx->tcs_shader) {
+ SELECT_SHADER_OR_FAIL(tcs);
+
+ UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
+ } else if (rctx->tes_shader) {
+ if (!rctx->fixed_func_tcs_shader) {
+ r600_generate_fixed_func_tcs(rctx);
+ if (!rctx->fixed_func_tcs_shader)
+ return false;
+
+ }
+ SELECT_SHADER_OR_FAIL(fixed_func_tcs);
+
+ UPDATE_SHADER(EG_HW_STAGE_HS, fixed_func_tcs);
+ } else
+ SET_NULL_SHADER(EG_HW_STAGE_HS);
+
+ if (rctx->tes_shader) {
+ SELECT_SHADER_OR_FAIL(tes);
+ }
+
+ SELECT_SHADER_OR_FAIL(vs);
+ if (rctx->gs_shader) {
if (!rctx->shader_stages.geom_enable) {
rctx->shader_stages.geom_enable = true;
- rctx->shader_stages.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
}
/* gs_shader provides GS and VS (copy shader) */
- if (unlikely(rctx->geometry_shader.shader != rctx->gs_shader->current)) {
- update_shader_atom(ctx, &rctx->geometry_shader, rctx->gs_shader->current);
- update_shader_atom(ctx, &rctx->vertex_shader, rctx->gs_shader->current->gs_copy_shader);
- /* Update clip misc state. */
- if (rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
- rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
- rctx->clip_misc_state.clip_disable != rctx->gs_shader->current->shader.vs_position_window_space) {
- rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->gs_shader->current->gs_copy_shader->pa_cl_vs_out_cntl;
- rctx->clip_misc_state.clip_dist_write = rctx->gs_shader->current->gs_copy_shader->shader.clip_dist_write;
- rctx->clip_misc_state.clip_disable = rctx->gs_shader->current->shader.vs_position_window_space;
- rctx->clip_misc_state.atom.dirty = true;
- }
- }
-
- r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
- if (unlikely(!rctx->vs_shader->current))
- return false;
+ UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
/* vs_shader is used as ES */
- if (unlikely(vs_dirty || rctx->export_shader.shader != rctx->vs_shader->current)) {
- update_shader_atom(ctx, &rctx->export_shader, rctx->vs_shader->current);
+
+ if (rctx->tes_shader) {
+ /* VS goes to LS, TES goes to ES */
+ UPDATE_SHADER(R600_HW_STAGE_ES, tes);
+ UPDATE_SHADER(EG_HW_STAGE_LS, vs);
+ } else {
+ /* vs_shader is used as ES */
+ UPDATE_SHADER(R600_HW_STAGE_ES, vs);
+ SET_NULL_SHADER(EG_HW_STAGE_LS);
}
} else {
- if (unlikely(rctx->geometry_shader.shader)) {
- update_shader_atom(ctx, &rctx->geometry_shader, NULL);
- update_shader_atom(ctx, &rctx->export_shader, NULL);
+ if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
+ SET_NULL_SHADER(R600_HW_STAGE_GS);
+ SET_NULL_SHADER(R600_HW_STAGE_ES);
rctx->shader_stages.geom_enable = false;
- rctx->shader_stages.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
}
- r600_shader_select(ctx, rctx->vs_shader, &vs_dirty);
- if (unlikely(!rctx->vs_shader->current))
- return false;
-
- if (unlikely(vs_dirty || rctx->vertex_shader.shader != rctx->vs_shader->current)) {
- update_shader_atom(ctx, &rctx->vertex_shader, rctx->vs_shader->current);
-
- /* Update clip misc state. */
- if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
- rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
- rctx->clip_misc_state.clip_disable != rctx->vs_shader->current->shader.vs_position_window_space) {
- rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
- rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
- rctx->clip_misc_state.clip_disable = rctx->vs_shader->current->shader.vs_position_window_space;
- rctx->clip_misc_state.atom.dirty = true;
- }
+ if (rctx->tes_shader) {
+ /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
+ UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, tes);
+ UPDATE_SHADER(EG_HW_STAGE_LS, vs);
+ } else {
+ SET_NULL_SHADER(EG_HW_STAGE_LS);
+ UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
}
}
- r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
- if (unlikely(!rctx->ps_shader->current))
- return false;
+ /* Update clip misc state. */
+ if (clip_so_current) {
+ r600_update_clip_state(rctx, clip_so_current);
+ rctx->b.streamout.enabled_stream_buffers_mask = clip_so_current->enabled_stream_buffers_mask;
+ }
- if (unlikely(ps_dirty || rctx->pixel_shader.shader != rctx->ps_shader->current ||
+ if (unlikely(ps_dirty || rctx->hw_shader_stages[R600_HW_STAGE_PS].shader != rctx->ps_shader->current ||
rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
- rctx->cb_misc_state.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
if (rctx->b.chip_class <= R700) {
if (rctx->cb_misc_state.multiwrite != multiwrite) {
rctx->cb_misc_state.multiwrite = multiwrite;
- rctx->cb_misc_state.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
}
- if (rctx->b.chip_class >= EVERGREEN) {
- evergreen_update_db_shader_control(rctx);
- } else {
- r600_update_db_shader_control(rctx);
- }
-
if (unlikely(!ps_dirty && rctx->ps_shader && rctx->rasterizer &&
((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
(rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)))) {
r600_update_ps_state(ctx, rctx->ps_shader->current);
}
- update_shader_atom(ctx, &rctx->pixel_shader, rctx->ps_shader->current);
+ r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
+ }
+ UPDATE_SHADER(R600_HW_STAGE_PS, ps);
+
+ if (rctx->b.chip_class >= EVERGREEN) {
+ evergreen_update_db_shader_control(rctx);
+ } else {
+ r600_update_db_shader_control(rctx);
}
/* on R600 we stuff masks + txq info into one constant buffer */
/* on evergreen we only need a txq info one */
- if (rctx->b.chip_class < EVERGREEN) {
- if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
- r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
- if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
- r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
- if (rctx->gs_shader && rctx->gs_shader->current->shader.uses_tex_buffers)
- r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
- } else {
- if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
- eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
- if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
- eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
- if (rctx->gs_shader && rctx->gs_shader->current->shader.uses_tex_buffers)
- eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
+ if (rctx->ps_shader) {
+ need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
+ if (need_buf_const) {
+ if (rctx->b.chip_class < EVERGREEN)
+ r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
+ else
+ eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
+ }
}
+ if (rctx->vs_shader) {
+ need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
+ if (need_buf_const) {
+ if (rctx->b.chip_class < EVERGREEN)
+ r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
+ else
+ eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
+ }
+ }
+
+ if (rctx->gs_shader) {
+ need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
+ if (need_buf_const) {
+ if (rctx->b.chip_class < EVERGREEN)
+ r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
+ else
+ eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
+ }
+ }
- if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
- r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
- if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
- r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
- if (rctx->gs_shader && rctx->gs_shader->current->shader.has_txq_cube_array_z_comp)
- r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_GEOMETRY);
+ r600_update_driver_const_buffers(rctx);
if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
if (!r600_adjust_gprs(rctx)) {
}
}
+ if (rctx->b.chip_class == EVERGREEN) {
+ if (!evergreen_adjust_gprs(rctx)) {
+ /* discard rendering */
+ return false;
+ }
+ }
+
blend_disable = (rctx->dual_src_blend &&
rctx->ps_shader->current->nr_ps_color_outputs < 2);
void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
struct r600_clip_misc_state *state = &rctx->clip_misc_state;
- r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
+ radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
state->pa_cl_clip_cntl |
(state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
S_028810_CLIP_DISABLE(state->clip_disable));
- r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
+ radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
state->pa_cl_vs_out_cntl |
(state->clip_plane_enable & state->clip_dist_write));
+ /* reuse needs to be set off if we write oViewport */
+ if (rctx->b.chip_class >= EVERGREEN)
+ radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
+ S_028AB4_REUSE_OFF(state->vs_out_viewport));
}
static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
struct r600_context *rctx = (struct r600_context *)ctx;
struct pipe_draw_info info = *dinfo;
struct pipe_index_buffer ib = {};
- unsigned i;
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
+ bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
+ uint64_t mask;
+ unsigned num_patches;
- if (!info.count && (info.indexed || !info.count_from_stream_output)) {
+ if (!info.indirect && !info.count && (info.indexed || !info.count_from_stream_output)) {
return;
}
}
/* make sure that the gfx ring is only one active */
- if (rctx->b.rings.dma.cs && rctx->b.rings.dma.cs->cdw) {
- rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
+ if (rctx->b.dma.cs && rctx->b.dma.cs->cdw) {
+ rctx->b.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
}
if (!r600_update_derived_state(rctx)) {
pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
ib.user_buffer = rctx->index_buffer.user_buffer;
ib.index_size = rctx->index_buffer.index_size;
- ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
+ ib.offset = rctx->index_buffer.offset;
+ if (!info.indirect) {
+ ib.offset += info.start * ib.index_size;
+ }
/* Translate 8-bit indices to 16-bit. */
- if (ib.index_size == 1) {
+ if (unlikely(ib.index_size == 1)) {
struct pipe_resource *out_buffer = NULL;
unsigned out_offset;
void *ptr;
+ unsigned start, count;
- u_upload_alloc(rctx->b.uploader, 0, info.count * 2,
+ if (likely(!info.indirect)) {
+ start = 0;
+ count = info.count;
+ }
+ else {
+ /* Have to get start/count from indirect buffer, slow path ahead... */
+ struct r600_resource *indirect_resource = (struct r600_resource *)info.indirect;
+ unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
+ PIPE_TRANSFER_READ);
+ if (data) {
+ data += info.indirect_offset / sizeof(unsigned);
+ start = data[2] * ib.index_size;
+ count = data[0];
+ }
+ else {
+ start = 0;
+ count = 0;
+ }
+ }
+
+ u_upload_alloc(rctx->b.uploader, start, count * 2, 256,
&out_offset, &out_buffer, &ptr);
util_shorten_ubyte_elts_to_userptr(
- &rctx->b.b, &ib, 0, ib.offset, info.count, ptr);
+ &rctx->b.b, &ib, 0, ib.offset + start, count, ptr);
pipe_resource_reference(&ib.buffer, NULL);
ib.user_buffer = NULL;
/* Upload the index buffer.
* The upload is skipped for small index counts on little-endian machines
* and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
+ * Indirect draws never use immediate indices.
* Note: Instanced rendering in combination with immediate indices hangs. */
- if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
- info.count*ib.index_size > 20)) {
+ if (ib.user_buffer && (R600_BIG_ENDIAN || info.indirect ||
+ info.instance_count > 1 ||
+ info.count*ib.index_size > 20)) {
u_upload_data(rctx->b.uploader, 0, info.count * ib.index_size,
ib.user_buffer, &ib.offset, &ib.buffer);
ib.user_buffer = NULL;
/* Set the index offset and primitive restart. */
if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
- rctx->vgt_state.vgt_indx_offset != info.index_bias) {
+ rctx->vgt_state.vgt_indx_offset != info.index_bias ||
+ (rctx->vgt_state.last_draw_was_indirect && !info.indirect)) {
rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
rctx->vgt_state.vgt_indx_offset = info.index_bias;
- rctx->vgt_state.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
}
/* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
if (rctx->b.chip_class == R600) {
rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
- rctx->cb_misc_state.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
+ if (rctx->b.chip_class >= EVERGREEN)
+ evergreen_setup_tess_constants(rctx, &info, &num_patches);
+
/* Emit states. */
r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
r600_flush_emit(rctx);
- for (i = 0; i < R600_NUM_ATOMS; i++) {
- if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
- continue;
- }
- r600_emit_atom(rctx, rctx->atoms[i]);
+ mask = rctx->dirty_atoms;
+ while (mask != 0) {
+ r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]);
}
if (rctx->b.chip_class == CAYMAN) {
rctx->b.streamout.prims_gen_query_enabled)
partial_vs_wave = true;
- r600_write_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
+ radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
}
+ if (rctx->b.chip_class >= EVERGREEN) {
+ uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, &info,
+ num_patches);
+
+ evergreen_set_ls_hs_config(rctx, cs, ls_hs_config);
+ evergreen_set_lds_alloc(rctx, cs, rctx->lds_alloc);
+ }
+
/* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
* even though it should have no effect on those. */
if (rctx->b.chip_class == R600 && rctx->rasterizer) {
unsigned prim = info.mode;
if (rctx->gs_shader) {
- prim = rctx->gs_shader->current->shader.gs_output_prim;
+ prim = rctx->gs_shader->gs_output_prim;
}
prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
info.mode == R600_PRIM_RECTANGLE_LIST) {
su_sc_mode_cntl &= C_028814_CULL_FRONT;
}
- r600_write_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
+ radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
}
/* Update start instance. */
- if (rctx->last_start_instance != info.start_instance) {
- r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
+ if (!info.indirect && rctx->last_start_instance != info.start_instance) {
+ radeon_set_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
rctx->last_start_instance = info.start_instance;
}
info.mode == PIPE_PRIM_LINE_LOOP)
ls_mask = 2;
- r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
+ radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
S_028A0C_AUTO_RESET_CNTL(ls_mask) |
(rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
- r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
+ radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
r600_conv_pipe_prim(info.mode));
rctx->last_primitive_type = info.mode;
}
/* Draw packets. */
- cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->b.predicate_drawing);
- cs->buf[cs->cdw++] = info.instance_count;
+ if (!info.indirect) {
+ cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, 0);
+ cs->buf[cs->cdw++] = info.instance_count;
+ }
+
+ if (unlikely(info.indirect)) {
+ uint64_t va = r600_resource(info.indirect)->gpu_address;
+ assert(rctx->b.chip_class >= EVERGREEN);
+
+ // Invalidate so non-indirect draw calls reset this state
+ rctx->vgt_state.last_draw_was_indirect = true;
+ rctx->last_start_instance = -1;
+
+ cs->buf[cs->cdw++] = PKT3(EG_PKT3_SET_BASE, 2, 0);
+ cs->buf[cs->cdw++] = EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE;
+ cs->buf[cs->cdw++] = va;
+ cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
+
+ cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+ cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
+ (struct r600_resource*)info.indirect,
+ RADEON_USAGE_READ,
+ RADEON_PRIO_DRAW_INDIRECT);
+ }
+
if (info.indexed) {
- cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->b.predicate_drawing);
+ cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, 0);
cs->buf[cs->cdw++] = ib.index_size == 4 ?
(VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
(VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
if (ib.user_buffer) {
unsigned size_bytes = info.count*ib.index_size;
unsigned size_dw = align(size_bytes, 4) / 4;
- cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->b.predicate_drawing);
+ cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit);
cs->buf[cs->cdw++] = info.count;
cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
cs->cdw += size_dw;
} else {
uint64_t va = r600_resource(ib.buffer)->gpu_address + ib.offset;
- cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->b.predicate_drawing);
- cs->buf[cs->cdw++] = va;
- cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
- cs->buf[cs->cdw++] = info.count;
- cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
- cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->b.predicate_drawing);
- cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
- (struct r600_resource*)ib.buffer,
- RADEON_USAGE_READ, RADEON_PRIO_MIN);
+
+ if (likely(!info.indirect)) {
+ cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit);
+ cs->buf[cs->cdw++] = va;
+ cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
+ cs->buf[cs->cdw++] = info.count;
+ cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
+ cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+ cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
+ (struct r600_resource*)ib.buffer,
+ RADEON_USAGE_READ,
+ RADEON_PRIO_INDEX_BUFFER);
+ }
+ else {
+ uint32_t max_size = (ib.buffer->width0 - ib.offset) / ib.index_size;
+
+ cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BASE, 1, 0);
+ cs->buf[cs->cdw++] = va;
+ cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
+
+ cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+ cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
+ (struct r600_resource*)ib.buffer,
+ RADEON_USAGE_READ,
+ RADEON_PRIO_INDEX_BUFFER);
+
+ cs->buf[cs->cdw++] = PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0);
+ cs->buf[cs->cdw++] = max_size;
+
+ cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit);
+ cs->buf[cs->cdw++] = info.indirect_offset;
+ cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
+ }
}
} else {
- if (info.count_from_stream_output) {
+ if (unlikely(info.count_from_stream_output)) {
struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
- r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
+ radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
cs->buf[cs->cdw++] = 0; /* unused */
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
- cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
+ cs->buf[cs->cdw++] = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
t->buf_filled_size, RADEON_USAGE_READ,
- RADEON_PRIO_MIN);
+ RADEON_PRIO_SO_FILLED_SIZE);
}
- cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->b.predicate_drawing);
- cs->buf[cs->cdw++] = info.count;
+ if (likely(!info.indirect)) {
+ cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit);
+ cs->buf[cs->cdw++] = info.count;
+ }
+ else {
+ cs->buf[cs->cdw++] = PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit);
+ cs->buf[cs->cdw++] = info.indirect_offset;
+ }
cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
(info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
}
+ /* SMX returns CONTEXT_DONE too early workaround */
+ if (rctx->b.family == CHIP_R600 ||
+ rctx->b.family == CHIP_RV610 ||
+ rctx->b.family == CHIP_RV630 ||
+ rctx->b.family == CHIP_RV635) {
+ /* if we have gs shader or streamout
+ we need to do a wait idle after every draw */
+ if (rctx->gs_shader || rctx->b.streamout.streamout_enabled) {
+ radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
+ }
+ }
+
+ /* ES ring rolling over at EOP - workaround */
+ if (rctx->b.chip_class == R600) {
+ cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
+ cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT);
+ }
+
if (rctx->screen->b.trace_bo) {
r600_trace_emit(rctx);
}
struct r600_texture *rtex = (struct r600_texture *)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
+
+ if (rtex->surface.flags & RADEON_SURF_SBUFFER)
+ rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
}
if (rctx->framebuffer.compressed_cb_mask) {
struct pipe_surface *surf;
void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
{
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
if (!shader)
r600_emit_command_buffer(cs, &shader->command_buffer);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
- radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo,
- RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA));
+ radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
+ RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER));
}
unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
if (rctx->db_misc_state.occlusion_query_enabled != enable) {
rctx->db_misc_state.occlusion_query_enabled = enable;
- rctx->db_misc_state.atom.dirty = true;
+ r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
}
}
rctx->b.b.create_fs_state = r600_create_ps_state;
rctx->b.b.create_vs_state = r600_create_vs_state;
rctx->b.b.create_gs_state = r600_create_gs_state;
+ rctx->b.b.create_tcs_state = r600_create_tcs_state;
+ rctx->b.b.create_tes_state = r600_create_tes_state;
rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
rctx->b.b.bind_blend_state = r600_bind_blend_state;
rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
rctx->b.b.bind_vs_state = r600_bind_vs_state;
rctx->b.b.bind_gs_state = r600_bind_gs_state;
+ rctx->b.b.bind_tcs_state = r600_bind_tcs_state;
+ rctx->b.b.bind_tes_state = r600_bind_tes_state;
rctx->b.b.delete_blend_state = r600_delete_blend_state;
rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
rctx->b.b.delete_fs_state = r600_delete_ps_state;
rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
rctx->b.b.delete_vs_state = r600_delete_vs_state;
rctx->b.b.delete_gs_state = r600_delete_gs_state;
+ rctx->b.b.delete_tcs_state = r600_delete_tcs_state;
+ rctx->b.b.delete_tes_state = r600_delete_tes_state;
rctx->b.b.set_blend_color = r600_set_blend_color;
rctx->b.b.set_clip_state = r600_set_clip_state;
rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
void r600_trace_emit(struct r600_context *rctx)
{
struct r600_screen *rscreen = rctx->screen;
- struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
uint64_t va;
uint32_t reloc;
va = rscreen->b.trace_bo->gpu_address;
- reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->b.trace_bo,
- RADEON_USAGE_READWRITE, RADEON_PRIO_MIN);
+ reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rscreen->b.trace_bo,
+ RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
radeon_emit(cs, va & 0xFFFFFFFFUL);
radeon_emit(cs, (va >> 32UL) & 0xFFUL);
projects / mesa.git / blobdiff