#include "util/u_index_modify.h"
#include "util/u_memory.h"
#include "util/u_upload_mgr.h"
+#include "util/u_math.h"
#include "tgsi/tgsi_parse.h"
-#include <byteswap.h>
#define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
{
+ assert(!cb->buf);
cb->buf = CALLOC(1, 4 * num_dw);
cb->max_num_dw = num_dw;
}
assert(id < R600_NUM_ATOMS);
assert(rctx->atoms[id] == NULL);
rctx->atoms[id] = atom;
- atom->id = id;
- atom->emit = emit;
+ atom->emit = (void*)emit;
atom->num_dw = num_dw;
atom->dirty = false;
}
void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
{
- r600_emit_command_buffer(rctx->rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
+ r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
}
void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
unsigned alpha_ref = a->sx_alpha_ref;
- if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
+ if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
alpha_ref &= ~0x1FFF;
}
{
struct r600_context *rctx = (struct r600_context *)ctx;
- rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
- rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
- rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
+ rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
+ R600_CONTEXT_FLUSH_AND_INV_CB |
+ R600_CONTEXT_FLUSH_AND_INV |
+ R600_CONTEXT_WAIT_3D_IDLE;
}
static unsigned r600_conv_pipe_prim(unsigned prim)
rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
update_cb = true;
}
- if (rctx->chip_class <= R700 &&
+ if (rctx->b.chip_class <= R700 &&
rctx->cb_misc_state.cb_color_control != color_control) {
rctx->cb_misc_state.cb_color_control = color_control;
update_cb = true;
void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct pipe_blend_color *state = &rctx->blend_color.state;
r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
- r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
- r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
- r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
- r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
+ radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
+ radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
+ radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
+ radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
}
void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
- r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, a->vgt_multi_prim_ib_reset_indx);
-}
-
-void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom)
-{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
- struct r600_vgt2_state *a = (struct r600_vgt2_state *)atom;
-
- r600_write_context_reg(cs, R_028408_VGT_INDX_OFFSET, a->vgt_indx_offset);
+ r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
+ radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
+ radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
}
static void r600_set_clip_state(struct pipe_context *ctx,
void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
- r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
+ radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
S_028430_STENCILREF(a->state.ref_value[0]) |
S_028430_STENCILMASK(a->state.valuemask[0]) |
S_028430_STENCILWRITEMASK(a->state.writemask[0]));
- r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
+ radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
S_028434_STENCILREF_BF(a->state.ref_value[1]) |
S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
ref.valuemask[1] = dsa->valuemask[1];
ref.writemask[0] = dsa->writemask[0];
ref.writemask[1] = dsa->writemask[1];
+ if (rctx->zwritemask != dsa->zwritemask) {
+ rctx->zwritemask = dsa->zwritemask;
+ if (rctx->b.chip_class >= EVERGREEN) {
+ /* work around some issue when not writting to zbuffer
+ * we are having lockup on evergreen so do not enable
+ * hyperz when not writting zbuffer
+ */
+ rctx->db_misc_state.atom.dirty = true;
+ }
+ }
r600_set_stencil_ref(ctx, &ref);
rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
rctx->alphatest_state.atom.dirty = true;
+ if (rctx->b.chip_class >= EVERGREEN) {
+ evergreen_update_db_shader_control(rctx);
+ } else {
+ r600_update_db_shader_control(rctx);
+ }
}
}
}
/* Workaround for a missing scissor enable on r600. */
- if (rctx->chip_class == R600 &&
+ if (rctx->b.chip_class == R600 &&
rs->scissor_enable != rctx->scissor.enable) {
rctx->scissor.enable = rs->scissor_enable;
rctx->scissor.atom.dirty = true;
{
if (state->dirty_mask) {
if (state->dirty_mask & state->has_bordercolor_mask) {
- rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
+ rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
}
state->atom.num_dw =
util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
r600_sampler_states_dirty(rctx, &dst->states);
/* Seamless cubemap state. */
- if (rctx->chip_class <= R700 &&
+ if (rctx->b.chip_class <= R700 &&
seamless_cube_map != -1 &&
seamless_cube_map != rctx->seamless_cube_map.enabled) {
/* change in TA_CNTL_AUX need a pipeline flush */
- rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
+ rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
rctx->seamless_cube_map.enabled = seamless_cube_map;
rctx->seamless_cube_map.atom.dirty = true;
}
if (ib) {
pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
- memcpy(&rctx->index_buffer, ib, sizeof(*ib));
+ memcpy(&rctx->index_buffer, ib, sizeof(*ib));
+ r600_context_add_resource_size(ctx, ib->buffer);
} else {
pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
}
void r600_vertex_buffers_dirty(struct r600_context *rctx)
{
if (rctx->vertex_buffer_state.dirty_mask) {
- rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
- rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
+ rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
+ rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
util_bitcount(rctx->vertex_buffer_state.dirty_mask);
rctx->vertex_buffer_state.atom.dirty = true;
}
vb[i].buffer_offset = input[i].buffer_offset;
pipe_resource_reference(&vb[i].buffer, input[i].buffer);
new_buffer_mask |= 1 << i;
+ r600_context_add_resource_size(ctx, input[i].buffer);
} else {
pipe_resource_reference(&vb[i].buffer, NULL);
disable_mask |= 1 << i;
struct r600_samplerview_state *state)
{
if (state->dirty_mask) {
- rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
- state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
+ rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
+ state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
util_bitcount(state->dirty_mask);
state->atom.dirty = true;
}
}
/* Changing from array to non-arrays textures and vice versa requires
* updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
- if (rctx->chip_class <= R700 &&
+ if (rctx->b.chip_class <= R700 &&
(dst->states.enabled_mask & (1 << i)) &&
(rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
new_mask |= 1 << i;
+ r600_context_add_resource_size(pipe, views[i]->texture);
} else {
pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
disable_mask |= 1 << i;
r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
}
-static void r600_set_viewport_state(struct pipe_context *ctx,
- const struct pipe_viewport_state *state)
+static void r600_set_viewport_states(struct pipe_context *ctx,
+ unsigned start_slot,
+ unsigned num_viewports,
+ const struct pipe_viewport_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct pipe_viewport_state *state = &rctx->viewport.state;
r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
- r600_write_value(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
- r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
- r600_write_value(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
- r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
- r600_write_value(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
- r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
+ radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
+ radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
+ radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
+ radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
+ radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
+ radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
}
/* Compute the key for the hw shader variant */
* (*dirty) is set to 1 if current variant was changed */
static int r600_shader_select(struct pipe_context *ctx,
struct r600_pipe_shader_selector* sel,
- unsigned *dirty)
+ bool *dirty)
{
struct r600_shader_key key;
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_shader * shader = NULL;
int r;
+ memset(&key, 0, sizeof(key));
key = r600_shader_selector_key(ctx, sel);
/* Check if we don't need to change anything.
R600_ERR("Failed to build shader variant (type=%u) %d\n",
sel->type, r);
sel->current = NULL;
+ FREE(shader);
return r;
}
key = r600_shader_selector_key(ctx, sel);
}
- shader->key = key;
+ memcpy(&shader->key, &key, sizeof(key));
sel->num_shaders++;
}
if (dirty)
- *dirty = 1;
+ *dirty = true;
shader->next_variant = sel->current;
sel->current = shader;
if (!state)
state = rctx->dummy_pixel_shader;
- rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
- r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
+ rctx->pixel_shader.shader = rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
+ rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
+ rctx->pixel_shader.atom.dirty = true;
- if (rctx->chip_class <= R700) {
+ r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo);
+
+ if (rctx->b.chip_class <= R700) {
bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
if (rctx->cb_misc_state.multiwrite != multiwrite) {
rctx->cb_misc_state.atom.dirty = true;
}
- if (rctx->chip_class >= EVERGREEN) {
+ if (rctx->b.chip_class >= EVERGREEN) {
evergreen_update_db_shader_control(rctx);
} else {
r600_update_db_shader_control(rctx);
{
struct r600_context *rctx = (struct r600_context *)ctx;
- rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
- if (state) {
- r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
+ if (!state)
+ return;
- /* Update clip misc state. */
- if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
- rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
- rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
- rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
- rctx->clip_misc_state.atom.dirty = true;
- }
+ rctx->vertex_shader.shader = rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
+ rctx->vertex_shader.atom.dirty = true;
+ rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
+
+ r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo);
+
+ /* Update clip misc state. */
+ if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
+ rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
+ rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
+ rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
+ rctx->clip_misc_state.atom.dirty = true;
}
}
void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
{
if (state->dirty_mask) {
- rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
- state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
+ rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
+ state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
: util_bitcount(state->dirty_mask)*19;
state->atom.dirty = true;
}
/* Note that the state tracker can unbind constant buffers by
* passing NULL here.
*/
- if (unlikely(!input)) {
+ if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
state->enabled_mask &= ~(1 << index);
state->dirty_mask &= ~(1 << index);
pipe_resource_reference(&state->cb[index].buffer, NULL);
}
for (i = 0; i < size / 4; ++i) {
- tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
+ tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
}
u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
} else {
u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
}
+ /* account it in gtt */
+ rctx->b.gtt += input->buffer_size;
} else {
/* Setup the hw buffer. */
cb->buffer_offset = input->buffer_offset;
pipe_resource_reference(&cb->buffer, input->buffer);
+ r600_context_add_resource_size(ctx, input->buffer);
}
state->enabled_mask |= 1 << index;
r600_constant_buffers_dirty(rctx, state);
}
-static struct pipe_stream_output_target *
-r600_create_so_target(struct pipe_context *ctx,
- struct pipe_resource *buffer,
- unsigned buffer_offset,
- unsigned buffer_size)
-{
- struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_so_target *t;
-
- t = CALLOC_STRUCT(r600_so_target);
- if (!t) {
- return NULL;
- }
-
- u_suballocator_alloc(rctx->allocator_so_filled_size, 4,
- &t->buf_filled_size_offset,
- (struct pipe_resource**)&t->buf_filled_size);
- if (!t->buf_filled_size) {
- FREE(t);
- return NULL;
- }
-
- t->b.reference.count = 1;
- t->b.context = ctx;
- pipe_resource_reference(&t->b.buffer, buffer);
- t->b.buffer_offset = buffer_offset;
- t->b.buffer_size = buffer_size;
- return &t->b;
-}
-
-static void r600_so_target_destroy(struct pipe_context *ctx,
- struct pipe_stream_output_target *target)
-{
- struct r600_so_target *t = (struct r600_so_target*)target;
- pipe_resource_reference(&t->b.buffer, NULL);
- pipe_resource_reference((struct pipe_resource**)&t->buf_filled_size, NULL);
- FREE(t);
-}
-
-static void r600_set_so_targets(struct pipe_context *ctx,
- unsigned num_targets,
- struct pipe_stream_output_target **targets,
- unsigned append_bitmask)
-{
- struct r600_context *rctx = (struct r600_context *)ctx;
- unsigned i;
-
- /* Stop streamout. */
- if (rctx->num_so_targets && !rctx->streamout_start) {
- r600_context_streamout_end(rctx);
- }
-
- /* Set the new targets. */
- for (i = 0; i < num_targets; i++) {
- pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
- }
- for (; i < rctx->num_so_targets; i++) {
- pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
- }
-
- rctx->num_so_targets = num_targets;
- rctx->streamout_start = num_targets != 0;
- rctx->streamout_append_bitmask = append_bitmask;
-}
-
static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
{
struct r600_context *rctx = (struct r600_context*)pipe;
cb.user_buffer = samplers->buffer_constants;
cb.buffer_offset = 0;
cb.buffer_size = array_size;
- rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
+ rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
pipe_resource_reference(&cb.buffer, NULL);
}
cb.user_buffer = samplers->buffer_constants;
cb.buffer_offset = 0;
cb.buffer_size = array_size;
- rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
+ rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
pipe_resource_reference(&cb.buffer, NULL);
}
cb.user_buffer = samplers->txq_constants;
cb.buffer_offset = 0;
cb.buffer_size = array_size;
- rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_TXQ_CONST_BUFFER, &cb);
+ rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_TXQ_CONST_BUFFER, &cb);
pipe_resource_reference(&cb.buffer, NULL);
}
static bool r600_update_derived_state(struct r600_context *rctx)
{
struct pipe_context * ctx = (struct pipe_context*)rctx;
- unsigned ps_dirty = 0;
+ bool ps_dirty = false;
bool blend_disable;
if (!rctx->blitter->running) {
((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
(rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
- if (rctx->chip_class >= EVERGREEN)
- evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
+ if (rctx->b.chip_class >= EVERGREEN)
+ evergreen_update_ps_state(ctx, rctx->ps_shader->current);
else
- r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
+ r600_update_ps_state(ctx, rctx->ps_shader->current);
- ps_dirty = 1;
+ ps_dirty = true;
}
- if (ps_dirty)
- r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
+ if (ps_dirty) {
+ rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
+ rctx->pixel_shader.atom.dirty = true;
+ }
/* on R600 we stuff masks + txq info into one constant buffer */
/* on evergreen we only need a txq info one */
- if (rctx->chip_class < EVERGREEN) {
+ if (rctx->b.chip_class < EVERGREEN) {
if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
- if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
+ if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
if (!r600_adjust_gprs(rctx)) {
/* discard rendering */
return false;
void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_clip_misc_state *state = &rctx->clip_misc_state;
r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
struct pipe_draw_info info = *dinfo;
struct pipe_index_buffer ib = {};
unsigned i;
- struct r600_block *dirty_block = NULL, *next_block = NULL;
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
if (!info.count && (info.indexed || !info.count_from_stream_output)) {
assert(0);
return;
}
+ /* make sure that the gfx ring is only one active */
+ if (rctx->b.rings.dma.cs) {
+ rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
+ }
+
if (!r600_update_derived_state(rctx)) {
/* useless to render because current rendering command
* can't be achieved
return;
}
- /* make sure that the gfx ring is only one active */
- rctx->rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
-
if (info.indexed) {
/* Initialize the index buffer struct. */
pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
&out_offset, &out_buffer, &ptr);
util_shorten_ubyte_elts_to_userptr(
- &rctx->context, &ib, 0, ib.offset, info.count, ptr);
+ &rctx->b.b, &ib, 0, ib.offset, info.count, ptr);
pipe_resource_reference(&ib.buffer, NULL);
ib.user_buffer = NULL;
info.index_bias = info.start;
}
- /* Enable stream out if needed. */
- if (rctx->streamout_start) {
- r600_context_streamout_begin(rctx);
- rctx->streamout_start = FALSE;
- }
-
- /* Set the index offset and multi primitive */
- if (rctx->vgt2_state.vgt_indx_offset != info.index_bias) {
- rctx->vgt2_state.vgt_indx_offset = info.index_bias;
- rctx->vgt2_state.atom.dirty = true;
- }
+ /* Set the index offset and primitive restart. */
if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
- rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index) {
+ rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
+ rctx->vgt_state.vgt_indx_offset != info.index_bias) {
rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
+ rctx->vgt_state.vgt_indx_offset = info.index_bias;
rctx->vgt_state.atom.dirty = true;
}
+ /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
+ if (rctx->b.chip_class == R600) {
+ rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
+ rctx->cb_misc_state.atom.dirty = true;
+ }
+
/* Emit states. */
r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
r600_flush_emit(rctx);
}
r600_emit_atom(rctx, rctx->atoms[i]);
}
- LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
- r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
- }
- rctx->pm4_dirty_cdwords = 0;
/* Update start instance. */
if (rctx->last_start_instance != info.start_instance) {
cs->buf[cs->cdw++] = info.count;
cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
- cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
+ cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
}
} else {
if (info.count_from_stream_output) {
struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
- uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
+ uint64_t va = r600_resource_va(&rctx->screen->b.b, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
cs->buf[cs->cdw++] = 0; /* unused */
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
- cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, &rctx->rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
+ cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
}
cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
(info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
}
-#if R600_TRACE_CS
if (rctx->screen->trace_bo) {
r600_trace_emit(rctx);
}
-#endif
/* Set the depth buffer as dirty. */
if (rctx->framebuffer.state.zsbuf) {
}
pipe_resource_reference(&ib.buffer, NULL);
+ rctx->num_draw_calls++;
}
void r600_draw_rectangle(struct blitter_context *blitter,
viewport.translate[1] = 0.0f;
viewport.translate[2] = 0.0f;
viewport.translate[3] = 0.0f;
- rctx->context.set_viewport_state(&rctx->context, &viewport);
+ rctx->b.b.set_viewport_states(&rctx->b.b, 0, 1, &viewport);
/* Upload vertices. The hw rectangle has only 3 vertices,
* I guess the 4th one is derived from the first 3.
}
/* draw */
- util_draw_vertex_buffer(&rctx->context, NULL, buf, rctx->blitter->vb_slot, offset,
+ util_draw_vertex_buffer(&rctx->b.b, NULL, buf, rctx->blitter->vb_slot, offset,
R600_PRIM_RECTANGLE_LIST, 3, 2);
pipe_resource_reference(&buf, NULL);
}
-void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
- struct r600_pipe_state *state,
- uint32_t offset, uint32_t value,
- uint32_t range_id, uint32_t block_id,
- struct r600_resource *bo,
- enum radeon_bo_usage usage)
-
-{
- struct r600_range *range;
- struct r600_block *block;
-
- if (bo) assert(usage);
-
- range = &ctx->range[range_id];
- block = range->blocks[block_id];
- state->regs[state->nregs].block = block;
- state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
-
- state->regs[state->nregs].value = value;
- state->regs[state->nregs].bo = bo;
- state->regs[state->nregs].bo_usage = usage;
-
- state->nregs++;
- assert(state->nregs < R600_BLOCK_MAX_REG);
-}
-
-void _r600_pipe_state_add_reg(struct r600_context *ctx,
- struct r600_pipe_state *state,
- uint32_t offset, uint32_t value,
- uint32_t range_id, uint32_t block_id)
-{
- _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
- range_id, block_id, NULL, 0);
-}
-
uint32_t r600_translate_stencil_op(int s_op)
{
switch (s_op) {
wrap_mode_uses_border_color(state->wrap_r, linear_filter));
}
+void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
+{
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
+ struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader->current;
+
+ r600_emit_command_buffer(cs, &shader->command_buffer);
+
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo, RADEON_USAGE_READ));
+}
+
/* keep this at the end of this file, please */
void r600_init_common_state_functions(struct r600_context *rctx)
{
- rctx->context.create_fs_state = r600_create_ps_state;
- rctx->context.create_vs_state = r600_create_vs_state;
- rctx->context.create_vertex_elements_state = r600_create_vertex_fetch_shader;
- rctx->context.bind_blend_state = r600_bind_blend_state;
- rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
- rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
- rctx->context.bind_fs_state = r600_bind_ps_state;
- rctx->context.bind_rasterizer_state = r600_bind_rs_state;
- rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
- rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
- rctx->context.bind_vs_state = r600_bind_vs_state;
- rctx->context.delete_blend_state = r600_delete_blend_state;
- rctx->context.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
- rctx->context.delete_fs_state = r600_delete_ps_state;
- rctx->context.delete_rasterizer_state = r600_delete_rs_state;
- rctx->context.delete_sampler_state = r600_delete_sampler_state;
- rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
- rctx->context.delete_vs_state = r600_delete_vs_state;
- rctx->context.set_blend_color = r600_set_blend_color;
- rctx->context.set_clip_state = r600_set_clip_state;
- rctx->context.set_constant_buffer = r600_set_constant_buffer;
- rctx->context.set_sample_mask = r600_set_sample_mask;
- rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
- rctx->context.set_viewport_state = r600_set_viewport_state;
- rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
- rctx->context.set_index_buffer = r600_set_index_buffer;
- rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
- rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
- rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
- rctx->context.texture_barrier = r600_texture_barrier;
- rctx->context.create_stream_output_target = r600_create_so_target;
- rctx->context.stream_output_target_destroy = r600_so_target_destroy;
- rctx->context.set_stream_output_targets = r600_set_so_targets;
- rctx->context.draw_vbo = r600_draw_vbo;
-}
-
-#if R600_TRACE_CS
+ rctx->b.b.create_fs_state = r600_create_ps_state;
+ rctx->b.b.create_vs_state = r600_create_vs_state;
+ rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
+ rctx->b.b.bind_blend_state = r600_bind_blend_state;
+ rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
+ rctx->b.b.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
+ rctx->b.b.bind_fs_state = r600_bind_ps_state;
+ rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
+ rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
+ rctx->b.b.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
+ rctx->b.b.bind_vs_state = r600_bind_vs_state;
+ rctx->b.b.delete_blend_state = r600_delete_blend_state;
+ rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
+ rctx->b.b.delete_fs_state = r600_delete_ps_state;
+ rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
+ rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
+ rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
+ rctx->b.b.delete_vs_state = r600_delete_vs_state;
+ rctx->b.b.set_blend_color = r600_set_blend_color;
+ rctx->b.b.set_clip_state = r600_set_clip_state;
+ rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
+ rctx->b.b.set_sample_mask = r600_set_sample_mask;
+ rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
+ rctx->b.b.set_viewport_states = r600_set_viewport_states;
+ rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
+ rctx->b.b.set_index_buffer = r600_set_index_buffer;
+ rctx->b.b.set_fragment_sampler_views = r600_set_ps_sampler_views;
+ rctx->b.b.set_vertex_sampler_views = r600_set_vs_sampler_views;
+ rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
+ rctx->b.b.texture_barrier = r600_texture_barrier;
+ rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
+ rctx->b.b.draw_vbo = r600_draw_vbo;
+}
+
void r600_trace_emit(struct r600_context *rctx)
{
struct r600_screen *rscreen = rctx->screen;
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
uint64_t va;
uint32_t reloc;
- va = r600_resource_va(&rscreen->screen, (void*)rscreen->trace_bo);
- reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
- r600_write_value(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
- r600_write_value(cs, va & 0xFFFFFFFFUL);
- r600_write_value(cs, (va >> 32UL) & 0xFFUL);
- r600_write_value(cs, cs->cdw);
- r600_write_value(cs, rscreen->cs_count);
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
- r600_write_value(cs, reloc);
-}
-#endif
+ va = r600_resource_va(&rscreen->b.b, (void*)rscreen->trace_bo);
+ reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
+ radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
+ radeon_emit(cs, va & 0xFFFFFFFFUL);
+ radeon_emit(cs, (va >> 32UL) & 0xFFUL);
+ radeon_emit(cs, cs->cdw);
+ radeon_emit(cs, rscreen->cs_count);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, reloc);
+}
projects / mesa.git / blobdiff