* Authors: Dave Airlie <airlied@redhat.com>
* Jerome Glisse <jglisse@redhat.com>
*/
-#include "util/u_blitter.h"
-#include "util/u_memory.h"
-#include "util/u_format.h"
-#include "pipebuffer/pb_buffer.h"
-#include "pipe/p_shader_tokens.h"
-#include "tgsi/tgsi_parse.h"
#include "r600_formats.h"
-#include "r600_pipe.h"
#include "r600d.h"
+#include "util/u_blitter.h"
+#include "util/u_upload_mgr.h"
+#include "tgsi/tgsi_parse.h"
+#include <byteswap.h>
+
static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->cs;
static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->cs;
- struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom;
+ struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
}
-static void r600_init_atom(struct r600_atom *atom,
- void (*emit)(struct r600_context *ctx, struct r600_atom *state),
- unsigned num_dw,
- enum r600_atom_flags flags)
+void r600_init_atom(struct r600_atom *atom,
+ void (*emit)(struct r600_context *ctx, struct r600_atom *state),
+ unsigned num_dw, enum r600_atom_flags flags)
{
atom->emit = emit;
atom->num_dw = num_dw;
atom->flags = flags;
}
+static void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
+ unsigned alpha_ref = a->sx_alpha_ref;
+
+ if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
+ alpha_ref &= ~0x1FFF;
+ }
+
+ r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
+ a->sx_alpha_test_control |
+ S_028410_ALPHA_TEST_BYPASS(a->bypass));
+ r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
+}
+
void r600_init_common_atoms(struct r600_context *rctx)
{
- r600_init_atom(&rctx->atom_surface_sync.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
- r600_init_atom(&rctx->atom_r6xx_flush_and_inv, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
+ r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
+ r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
+ r600_init_atom(&rctx->alphatest_state.atom, r600_emit_alphatest_state, 3, 0);
+ r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
}
unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
- r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
+ rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
+ r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
}
static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
struct r600_pipe_state *rstate;
+ bool update_cb = false;
if (state == NULL)
return;
rstate = &blend->rstate;
rctx->states[rstate->id] = rstate;
- rctx->cb_target_mask = blend->cb_target_mask;
-
- /* Replace every bit except MULTIWRITE_ENABLE. */
- rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
- rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
-
+ rctx->dual_src_blend = blend->dual_src_blend;
+ rctx->alpha_to_one = blend->alpha_to_one;
r600_context_pipe_state_set(rctx, rstate);
+
+ if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
+ rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
+ update_cb = true;
+ }
+ if (rctx->chip_class <= R700 &&
+ rctx->cb_misc_state.cb_color_control != blend->cb_color_control) {
+ rctx->cb_misc_state.cb_color_control = blend->cb_color_control;
+ update_cb = true;
+ }
+ if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
+ rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
+ update_cb = true;
+ }
+ if (update_cb) {
+ r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
+ }
}
void r600_set_blend_color(struct pipe_context *ctx,
return;
rstate->id = R600_PIPE_STATE_BLEND_COLOR;
- r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
+ r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
+ r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
+ r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
R_028430_DB_STENCILREFMASK,
S_028430_STENCILREF(state->ref_value[0]) |
S_028430_STENCILMASK(state->valuemask[0]) |
- S_028430_STENCILWRITEMASK(state->writemask[0]),
- NULL, 0);
+ S_028430_STENCILWRITEMASK(state->writemask[0]));
r600_pipe_state_add_reg(rstate,
R_028434_DB_STENCILREFMASK_BF,
S_028434_STENCILREF_BF(state->ref_value[1]) |
S_028434_STENCILMASK_BF(state->valuemask[1]) |
- S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
- NULL, 0);
+ S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
return;
rstate = &dsa->rstate;
rctx->states[rstate->id] = rstate;
- rctx->alpha_ref = dsa->alpha_ref;
- rctx->alpha_ref_dirty = true;
r600_context_pipe_state_set(rctx, rstate);
ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
ref.writemask[1] = dsa->writemask[1];
r600_set_stencil_ref(ctx, &ref);
+
+ /* Update alphatest state. */
+ if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
+ rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
+ rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
+ rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
+ r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
+ }
+}
+
+void r600_set_max_scissor(struct r600_context *rctx)
+{
+ /* Set a scissor state such that it doesn't do anything. */
+ struct pipe_scissor_state scissor;
+ scissor.minx = 0;
+ scissor.miny = 0;
+ scissor.maxx = 8192;
+ scissor.maxy = 8192;
+
+ r600_set_scissor_state(rctx, &scissor);
}
void r600_bind_rs_state(struct pipe_context *ctx, void *state)
rctx->two_side = rs->two_side;
rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
+ rctx->multisample_enable = rs->multisample_enable;
rctx->rasterizer = rs;
} else {
r600_polygon_offset_update(rctx);
}
+
+ /* Workaround for a missing scissor enable on r600. */
+ if (rctx->chip_class == R600) {
+ if (rs->scissor_enable != rctx->scissor_enable) {
+ rctx->scissor_enable = rs->scissor_enable;
+
+ if (rs->scissor_enable) {
+ r600_set_scissor_state(rctx, &rctx->scissor_state);
+ } else {
+ r600_set_max_scissor(rctx);
+ }
+ }
+ }
}
void r600_delete_rs_state(struct pipe_context *ctx, void *state)
FREE(resource);
}
+static void r600_bind_samplers(struct r600_context *rctx,
+ struct r600_textures_info *dst,
+ unsigned count, void **states)
+{
+ int seamless_cube_map = -1;
+ unsigned i;
+
+ memcpy(dst->samplers, states, sizeof(void*) * count);
+ dst->n_samplers = count;
+ dst->atom_sampler.num_dw = 0;
+
+ for (i = 0; i < count; i++) {
+ struct r600_pipe_sampler_state *sampler = states[i];
+
+ if (sampler == NULL) {
+ continue;
+ }
+ if (sampler->border_color_use) {
+ dst->atom_sampler.num_dw += 11;
+ rctx->flags |= R600_PARTIAL_FLUSH;
+ } else {
+ dst->atom_sampler.num_dw += 5;
+ }
+ seamless_cube_map = sampler->seamless_cube_map;
+ }
+ if (rctx->chip_class <= R700 && seamless_cube_map != -1 && seamless_cube_map != rctx->seamless_cube_map.enabled) {
+ /* change in TA_CNTL_AUX need a pipeline flush */
+ rctx->flags |= R600_PARTIAL_FLUSH;
+ rctx->seamless_cube_map.enabled = seamless_cube_map;
+ r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
+ }
+ if (dst->atom_sampler.num_dw) {
+ r600_atom_dirty(rctx, &dst->atom_sampler);
+ }
+}
+
+void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
+}
+
+void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
+}
+
+void r600_delete_sampler(struct pipe_context *ctx, void *state)
+{
+ free(state);
+}
+
void r600_delete_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
rctx->vertex_elements = v;
if (v) {
r600_inval_shader_cache(rctx);
- u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
- v->vmgr_elements);
rctx->states[v->rstate.id] = &v->rstate;
r600_context_pipe_state_set(rctx, &v->rstate);
rctx->vertex_elements = NULL;
pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
- u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
FREE(state);
}
-
void r600_set_index_buffer(struct pipe_context *ctx,
const struct pipe_index_buffer *ib)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
+ if (ib) {
+ pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
+ memcpy(&rctx->index_buffer, ib, sizeof(*ib));
+ } else {
+ pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
+ }
+}
+
+void r600_vertex_buffers_dirty(struct r600_context *rctx)
+{
+ if (rctx->vertex_buffer_state.dirty_mask) {
+ r600_inval_vertex_cache(rctx);
+ rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
+ util_bitcount(rctx->vertex_buffer_state.dirty_mask);
+ r600_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
+ }
}
void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
- const struct pipe_vertex_buffer *buffers)
+ const struct pipe_vertex_buffer *input)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- int i;
+ struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
+ struct pipe_vertex_buffer *vb = state->vb;
+ unsigned i;
+ /* This sets 1-bit for buffers with index >= count. */
+ uint32_t disable_mask = ~((1ull << count) - 1);
+ /* These are the new buffers set by this function. */
+ uint32_t new_buffer_mask = 0;
+
+ /* Set buffers with index >= count to NULL. */
+ uint32_t remaining_buffers_mask =
+ rctx->vertex_buffer_state.enabled_mask & disable_mask;
+
+ while (remaining_buffers_mask) {
+ i = u_bit_scan(&remaining_buffers_mask);
+ pipe_resource_reference(&vb[i].buffer, NULL);
+ }
- /* Zero states. */
+ /* Set vertex buffers. */
for (i = 0; i < count; i++) {
- if (!buffers[i].buffer) {
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
+ if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
+ if (input[i].buffer) {
+ vb[i].stride = input[i].stride;
+ vb[i].buffer_offset = input[i].buffer_offset;
+ pipe_resource_reference(&vb[i].buffer, input[i].buffer);
+ new_buffer_mask |= 1 << i;
} else {
- r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
+ pipe_resource_reference(&vb[i].buffer, NULL);
+ disable_mask |= 1 << i;
}
}
+ }
+
+ rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
+ rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
+ rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
+ rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
+
+ r600_vertex_buffers_dirty(rctx);
+}
+
+void r600_sampler_views_dirty(struct r600_context *rctx,
+ struct r600_samplerview_state *state)
+{
+ if (state->dirty_mask) {
+ r600_inval_texture_cache(rctx);
+ state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
+ util_bitcount(state->dirty_mask);
+ r600_atom_dirty(rctx, &state->atom);
}
- for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
+}
+
+void r600_set_sampler_views(struct r600_context *rctx,
+ struct r600_textures_info *dst,
+ unsigned count,
+ struct pipe_sampler_view **views)
+{
+ struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
+ unsigned i;
+ /* This sets 1-bit for textures with index >= count. */
+ uint32_t disable_mask = ~((1ull << count) - 1);
+ /* These are the new textures set by this function. */
+ uint32_t new_mask = 0;
+
+ /* Set textures with index >= count to NULL. */
+ uint32_t remaining_mask = dst->views.enabled_mask & disable_mask;
+
+ while (remaining_mask) {
+ i = u_bit_scan(&remaining_mask);
+ assert(dst->views.views[i]);
+
+ pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
+ }
+
+ for (i = 0; i < count; i++) {
+ if (rviews[i] == dst->views.views[i]) {
+ continue;
+ }
+
+ if (rviews[i]) {
+ struct r600_resource_texture *rtex =
+ (struct r600_resource_texture*)rviews[i]->base.texture;
+
+ if (rtex->is_depth && !rtex->is_flushing_texture) {
+ dst->views.depth_texture_mask |= 1 << i;
+ } else {
+ dst->views.depth_texture_mask &= ~(1 << i);
+ }
+
+ /* Changing from array to non-arrays textures and vice
+ * versa requires updating TEX_ARRAY_OVERRIDE on R6xx-R7xx. */
+ if (rctx->chip_class <= R700 &&
+ (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
+ rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
+ r600_atom_dirty(rctx, &dst->atom_sampler);
+ }
+
+ pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
+ new_mask |= 1 << i;
} else {
- r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
+ pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
+ disable_mask |= 1 << i;
}
}
- u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
+ dst->views.enabled_mask &= ~disable_mask;
+ dst->views.dirty_mask &= dst->views.enabled_mask;
+ dst->views.enabled_mask |= new_mask;
+ dst->views.dirty_mask |= new_mask;
+ dst->views.depth_texture_mask &= dst->views.enabled_mask;
+
+ r600_sampler_views_dirty(rctx, &dst->views);
}
void *r600_create_vertex_elements(struct pipe_context *ctx,
return NULL;
v->count = count;
- v->vmgr_elements =
- u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
- elements, v->elements);
+ memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
FREE(v);
return v;
}
-void *r600_create_shader_state(struct pipe_context *ctx,
- const struct pipe_shader_state *state)
+/* Compute the key for the hw shader variant */
+static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx,
+ struct r600_pipe_shader_selector * sel)
{
- struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ unsigned key;
+
+ if (sel->type == PIPE_SHADER_FRAGMENT) {
+ key = rctx->two_side |
+ ((rctx->alpha_to_one && rctx->multisample_enable && !rctx->cb0_is_integer) << 1) |
+ (MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 2);
+ } else
+ key = 0;
+
+ return key;
+}
+
+/* Select the hw shader variant depending on the current state.
+ * (*dirty) is set to 1 if current variant was changed */
+static int r600_shader_select(struct pipe_context *ctx,
+ struct r600_pipe_shader_selector* sel,
+ unsigned *dirty)
+{
+ unsigned key;
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_pipe_shader * shader = NULL;
int r;
- shader->tokens = tgsi_dup_tokens(state->tokens);
- shader->so = state->stream_output;
+ key = r600_shader_selector_key(ctx, sel);
- r = r600_pipe_shader_create(ctx, shader);
- if (r) {
- return NULL;
+ /* Check if we don't need to change anything.
+ * This path is also used for most shaders that don't need multiple
+ * variants, it will cost just a computation of the key and this
+ * test. */
+ if (likely(sel->current && sel->current->key == key)) {
+ return 0;
}
- return shader;
+
+ /* lookup if we have other variants in the list */
+ if (sel->num_shaders > 1) {
+ struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
+
+ while (c && c->key != key) {
+ p = c;
+ c = c->next_variant;
+ }
+
+ if (c) {
+ p->next_variant = c->next_variant;
+ shader = c;
+ }
+ }
+
+ if (unlikely(!shader)) {
+ shader = CALLOC(1, sizeof(struct r600_pipe_shader));
+ shader->selector = sel;
+
+ r = r600_pipe_shader_create(ctx, shader);
+ if (unlikely(r)) {
+ R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
+ sel->type, key, r);
+ sel->current = NULL;
+ return r;
+ }
+
+ /* We don't know the value of nr_ps_max_color_exports until we built
+ * at least one variant, so we may need to recompute the key after
+ * building first variant. */
+ if (sel->type == PIPE_SHADER_FRAGMENT &&
+ sel->num_shaders == 0) {
+ sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
+ key = r600_shader_selector_key(ctx, sel);
+ }
+
+ shader->key = key;
+ sel->num_shaders++;
+ }
+
+ if (dirty)
+ *dirty = 1;
+
+ shader->next_variant = sel->current;
+ sel->current = shader;
+
+ if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
+ r600_adjust_gprs(rctx);
+ }
+
+ if (rctx->ps_shader &&
+ rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
+ rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
+ r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
+ }
+ return 0;
+}
+
+static void *r600_create_shader_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state,
+ unsigned pipe_shader_type)
+{
+ struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
+ int r;
+
+ sel->type = pipe_shader_type;
+ sel->tokens = tgsi_dup_tokens(state->tokens);
+ sel->so = state->stream_output;
+
+ r = r600_shader_select(ctx, sel, NULL);
+ if (r)
+ return NULL;
+
+ return sel;
+}
+
+void *r600_create_shader_state_ps(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
+}
+
+void *r600_create_shader_state_vs(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
}
void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- /* TODO delete old shader */
- rctx->ps_shader = (struct r600_pipe_shader *)state;
- if (state) {
- r600_inval_shader_cache(rctx);
- r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
+ if (!state)
+ state = rctx->dummy_pixel_shader;
+
+ rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
+ r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
- rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
- rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
+ if (rctx->chip_class <= R700) {
+ bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
+
+ if (rctx->cb_misc_state.multiwrite != multiwrite) {
+ rctx->cb_misc_state.multiwrite = multiwrite;
+ r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
+ }
+
+ if (rctx->vs_shader)
+ r600_adjust_gprs(rctx);
}
- if (rctx->ps_shader && rctx->vs_shader) {
- r600_adjust_gprs(rctx);
+
+ if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
+ rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
+ r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
}
}
{
struct r600_context *rctx = (struct r600_context *)ctx;
- /* TODO delete old shader */
- rctx->vs_shader = (struct r600_pipe_shader *)state;
+ rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
if (state) {
- r600_inval_shader_cache(rctx);
- r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
+ r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
+
+ if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
+ r600_adjust_gprs(rctx);
}
- if (rctx->ps_shader && rctx->vs_shader) {
- r600_adjust_gprs(rctx);
+}
+
+static void r600_delete_shader_selector(struct pipe_context *ctx,
+ struct r600_pipe_shader_selector *sel)
+{
+ struct r600_pipe_shader *p = sel->current, *c;
+ while (p) {
+ c = p->next_variant;
+ r600_pipe_shader_destroy(ctx, p);
+ free(p);
+ p = c;
}
+
+ free(sel->tokens);
+ free(sel);
}
+
void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
+ struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
- if (rctx->ps_shader == shader) {
+ if (rctx->ps_shader == sel) {
rctx->ps_shader = NULL;
}
- free(shader->tokens);
- r600_pipe_shader_destroy(ctx, shader);
- free(shader);
+ r600_delete_shader_selector(ctx, sel);
}
void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
+ struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
- if (rctx->vs_shader == shader) {
+ if (rctx->vs_shader == sel) {
rctx->vs_shader = NULL;
}
- free(shader->tokens);
- r600_pipe_shader_destroy(ctx, shader);
- free(shader);
+ r600_delete_shader_selector(ctx, sel);
}
-static void r600_update_alpha_ref(struct r600_context *rctx)
+void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
{
- unsigned alpha_ref;
- struct r600_pipe_state rstate;
-
- alpha_ref = rctx->alpha_ref;
- rstate.nregs = 0;
- if (rctx->export_16bpc)
- alpha_ref &= ~0x1FFF;
- r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
-
- r600_context_pipe_state_set(rctx, &rstate);
- rctx->alpha_ref_dirty = false;
+ if (state->dirty_mask) {
+ r600_inval_shader_cache(rctx);
+ state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
+ : util_bitcount(state->dirty_mask)*19;
+ r600_atom_dirty(rctx, &state->atom);
+ }
}
void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
- struct pipe_resource *buffer)
+ struct pipe_constant_buffer *input)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_resource *rbuffer = r600_resource(buffer);
- struct r600_pipe_resource_state *rstate;
- uint64_t va_offset;
- uint32_t offset;
+ struct r600_constbuf_state *state;
+ struct pipe_constant_buffer *cb;
+ const uint8_t *ptr;
+
+ switch (shader) {
+ case PIPE_SHADER_VERTEX:
+ state = &rctx->vs_constbuf_state;
+ break;
+ case PIPE_SHADER_FRAGMENT:
+ state = &rctx->ps_constbuf_state;
+ break;
+ default:
+ return;
+ }
/* Note that the state tracker can unbind constant buffers by
* passing NULL here.
*/
- if (buffer == NULL) {
+ if (unlikely(!input)) {
+ state->enabled_mask &= ~(1 << index);
+ state->dirty_mask &= ~(1 << index);
+ pipe_resource_reference(&state->cb[index].buffer, NULL);
return;
}
- r600_inval_shader_cache(rctx);
+ cb = &state->cb[index];
+ cb->buffer_size = input->buffer_size;
- r600_upload_const_buffer(rctx, &rbuffer, &offset);
- va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
- va_offset += offset;
- va_offset >>= 8;
+ ptr = input->user_buffer;
- switch (shader) {
- case PIPE_SHADER_VERTEX:
- rctx->vs_const_buffer.nregs = 0;
- r600_pipe_state_add_reg(&rctx->vs_const_buffer,
- R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
- ALIGN_DIVUP(buffer->width0 >> 4, 16),
- NULL, 0);
- r600_pipe_state_add_reg(&rctx->vs_const_buffer,
- R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
- va_offset, rbuffer, RADEON_USAGE_READ);
- r600_context_pipe_state_set(rctx, &rctx->vs_const_buffer);
-
- rstate = &rctx->vs_const_buffer_resource[index];
- if (!rstate->id) {
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_init_buffer_resource(rctx, rstate);
- } else {
- r600_pipe_init_buffer_resource(rctx, rstate);
+ if (ptr) {
+ /* Upload the user buffer. */
+ if (R600_BIG_ENDIAN) {
+ uint32_t *tmpPtr;
+ unsigned i, size = input->buffer_size;
+
+ if (!(tmpPtr = malloc(size))) {
+ R600_ERR("Failed to allocate BE swap buffer.\n");
+ return;
}
- }
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
- evergreen_context_pipe_state_set_vs_resource(rctx, rstate, index);
- } else {
- r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
- r600_context_pipe_state_set_vs_resource(rctx, rstate, index);
- }
- break;
- case PIPE_SHADER_FRAGMENT:
- rctx->ps_const_buffer.nregs = 0;
- r600_pipe_state_add_reg(&rctx->ps_const_buffer,
- R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
- ALIGN_DIVUP(buffer->width0 >> 4, 16),
- NULL, 0);
- r600_pipe_state_add_reg(&rctx->ps_const_buffer,
- R_028940_ALU_CONST_CACHE_PS_0,
- va_offset, rbuffer, RADEON_USAGE_READ);
- r600_context_pipe_state_set(rctx, &rctx->ps_const_buffer);
-
- rstate = &rctx->ps_const_buffer_resource[index];
- if (!rstate->id) {
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_init_buffer_resource(rctx, rstate);
- } else {
- r600_pipe_init_buffer_resource(rctx, rstate);
+ for (i = 0; i < size / 4; ++i) {
+ tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
}
- }
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
- evergreen_context_pipe_state_set_ps_resource(rctx, rstate, index);
+
+ u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
+ free(tmpPtr);
} else {
- r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
- r600_context_pipe_state_set_ps_resource(rctx, rstate, index);
+ u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
}
- break;
- default:
- R600_ERR("unsupported %d\n", shader);
- return;
+ } else {
+ /* Setup the hw buffer. */
+ cb->buffer_offset = input->buffer_offset;
+ pipe_resource_reference(&cb->buffer, input->buffer);
}
- if (buffer != &rbuffer->b.b.b)
- pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
+ state->enabled_mask |= 1 << index;
+ state->dirty_mask |= 1 << index;
+ r600_constant_buffers_dirty(rctx, state);
}
struct pipe_stream_output_target *
t->filled_size = (struct r600_resource*)
pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
- ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
+ ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
memset(ptr, 0, t->filled_size->buf->size);
- rctx->ws->buffer_unmap(t->filled_size->buf);
+ rctx->ws->buffer_unmap(t->filled_size->cs_buf);
return &t->b;
}
unsigned i;
/* Stop streamout. */
- if (rctx->num_so_targets) {
+ if (rctx->num_so_targets && !rctx->streamout_start) {
r600_context_streamout_end(rctx);
}
rctx->streamout_append_bitmask = append_bitmask;
}
-static void r600_vertex_buffer_update(struct r600_context *rctx)
+void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
{
- struct r600_pipe_resource_state *rstate;
- struct r600_resource *rbuffer;
- struct pipe_vertex_buffer *vertex_buffer;
- unsigned i, count, offset;
-
- r600_inval_vertex_cache(rctx);
-
- if (rctx->vertex_elements->vbuffer_need_offset) {
- /* one resource per vertex elements */
- count = rctx->vertex_elements->count;
- } else {
- /* bind vertex buffer once */
- count = rctx->vbuf_mgr->nr_real_vertex_buffers;
- }
-
- for (i = 0 ; i < count; i++) {
- rstate = &rctx->fs_resource[i];
+ struct r600_context *rctx = (struct r600_context*)pipe;
- if (rctx->vertex_elements->vbuffer_need_offset) {
- /* one resource per vertex elements */
- unsigned vbuffer_index;
- vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
- vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
- rbuffer = (struct r600_resource*)vertex_buffer->buffer;
- offset = rctx->vertex_elements->vbuffer_offset[i];
- } else {
- /* bind vertex buffer once */
- vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
- rbuffer = (struct r600_resource*)vertex_buffer->buffer;
- offset = 0;
- }
- if (vertex_buffer == NULL || rbuffer == NULL)
- continue;
- offset += vertex_buffer->buffer_offset;
-
- if (!rstate->id) {
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_init_buffer_resource(rctx, rstate);
- } else {
- r600_pipe_init_buffer_resource(rctx, rstate);
- }
- }
-
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
- evergreen_context_pipe_state_set_fs_resource(rctx, rstate, i);
- } else {
- r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
- r600_context_pipe_state_set_fs_resource(rctx, rstate, i);
- }
- }
-}
-
-static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
-{
- struct r600_context *rctx = (struct r600_context *)ctx;
- int r;
-
- r600_pipe_shader_destroy(ctx, shader);
- r = r600_pipe_shader_create(ctx, shader);
- if (r) {
- return r;
- }
- r600_context_pipe_state_set(rctx, &shader->rstate);
+ if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
+ return;
- return 0;
+ rctx->sample_mask.sample_mask = sample_mask;
+ r600_atom_dirty(rctx, &rctx->sample_mask.atom);
}
static void r600_update_derived_state(struct r600_context *rctx)
{
struct pipe_context * ctx = (struct pipe_context*)rctx;
- struct r600_pipe_state rstate;
-
- rstate.nregs = 0;
-
- if (rstate.nregs)
- r600_context_pipe_state_set(rctx, &rstate);
+ unsigned ps_dirty = 0;
if (!rctx->blitter->running) {
- if (rctx->have_depth_fb || rctx->have_depth_texture)
- r600_flush_depth_textures(rctx);
- }
-
- if (rctx->chip_class < EVERGREEN) {
- r600_update_sampler_states(rctx);
- }
-
- if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
- ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
- (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
- r600_shader_rebuild(&rctx->context, rctx->ps_shader);
+ /* Flush depth textures which need to be flushed. */
+ if (rctx->vs_samplers.views.depth_texture_mask) {
+ r600_flush_depth_textures(rctx, &rctx->vs_samplers.views);
+ }
+ if (rctx->ps_samplers.views.depth_texture_mask) {
+ r600_flush_depth_textures(rctx, &rctx->ps_samplers.views);
+ }
}
- if (rctx->alpha_ref_dirty) {
- r600_update_alpha_ref(rctx);
- }
+ r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
- (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
- (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
+ (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
+ (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
if (rctx->chip_class >= EVERGREEN)
- evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
+ evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
else
- r600_pipe_shader_ps(ctx, rctx->ps_shader);
+ r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
- r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
+ ps_dirty = 1;
}
+ if (ps_dirty)
+ r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
+
+ if (rctx->chip_class >= EVERGREEN) {
+ evergreen_update_dual_export_state(rctx);
+ } else {
+ r600_update_dual_export_state(rctx);
+ }
+}
+
+static unsigned r600_conv_prim_to_gs_out(unsigned mode)
+{
+ static const int prim_conv[] = {
+ V_028A6C_OUTPRIM_TYPE_POINTLIST,
+ V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP
+ };
+ assert(mode < Elements(prim_conv));
+
+ return prim_conv[mode];
}
void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
struct pipe_draw_info info = *dinfo;
- struct r600_draw rdraw = {};
struct pipe_index_buffer ib = {};
- unsigned prim, mask, ls_mask = 0;
+ unsigned prim, ls_mask = 0;
struct r600_block *dirty_block = NULL, *next_block = NULL;
struct r600_atom *state = NULL, *next_state = NULL;
+ struct radeon_winsys_cs *cs = rctx->cs;
+ uint64_t va;
+ uint8_t *ptr;
if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
- (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
!r600_conv_pipe_prim(info.mode, &prim)) {
+ assert(0);
return;
}
- if (!rctx->ps_shader || !rctx->vs_shader)
+ if (!rctx->vs_shader) {
+ assert(0);
return;
+ }
r600_update_derived_state(rctx);
- u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
- r600_vertex_buffer_update(rctx);
-
- rdraw.vgt_num_indices = info.count;
- rdraw.vgt_num_instances = info.instance_count;
+ /* partial flush triggered by border color change */
+ if (rctx->flags & R600_PARTIAL_FLUSH) {
+ rctx->flags &= ~R600_PARTIAL_FLUSH;
+ r600_write_value(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ r600_write_value(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
+ }
if (info.indexed) {
/* Initialize the index buffer struct. */
- pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
- ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
- ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
+ pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
+ ib.user_buffer = rctx->index_buffer.user_buffer;
+ ib.index_size = rctx->index_buffer.index_size;
+ ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
/* Translate or upload, if needed. */
r600_translate_index_buffer(rctx, &ib, info.count);
- if (u_vbuf_resource(ib.buffer)->user_ptr) {
- r600_upload_index_buffer(rctx, &ib, info.count);
+ ptr = (uint8_t*)ib.user_buffer;
+ if (!ib.buffer && ptr) {
+ u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
+ ptr, &ib.offset, &ib.buffer);
}
-
- /* Initialize the r600_draw struct with index buffer info. */
- if (ib.index_size == 4) {
- rdraw.vgt_index_type = VGT_INDEX_32 |
- (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0);
- } else {
- rdraw.vgt_index_type = VGT_INDEX_16 |
- (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0);
- }
- rdraw.indices = (struct r600_resource*)ib.buffer;
- rdraw.indices_bo_offset = ib.offset;
- rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
} else {
info.index_bias = info.start;
- rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
- if (info.count_from_stream_output) {
- rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
-
- r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
- }
}
- mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
-
if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
rctx->vgt.id = R600_PIPE_STATE_VGT;
rctx->vgt.nregs = 0;
- r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
- if (rctx->chip_class <= R700)
- r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
+ r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
+ r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
}
rctx->vgt.nregs = 0;
r600_pipe_state_mod_reg(&rctx->vgt, prim);
- r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
+ r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
if (prim == V_008958_DI_PT_LINELIST)
ls_mask = 1;
- else if (prim == V_008958_DI_PT_LINESTRIP)
+ else if (prim == V_008958_DI_PT_LINESTRIP ||
+ prim == V_008958_DI_PT_LINELOOP)
ls_mask = 2;
r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
- if (rctx->chip_class <= R700)
- r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
r600_pipe_state_mod_reg(&rctx->vgt,
- rctx->vs_shader->pa_cl_vs_out_cntl |
- (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
+ rctx->vs_shader->current->pa_cl_vs_out_cntl |
+ (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
r600_pipe_state_mod_reg(&rctx->vgt,
rctx->pa_cl_clip_cntl |
- (rctx->vs_shader->shader.clip_dist_write ||
- rctx->vs_shader->shader.vs_prohibit_ucps ?
+ (rctx->vs_shader->current->shader.clip_dist_write ||
+ rctx->vs_shader->current->shader.vs_prohibit_ucps ?
0 : rctx->rasterizer->clip_plane_enable & 0x3F));
r600_context_pipe_state_set(rctx, &rctx->vgt);
- rdraw.db_render_override = dsa->db_render_override;
- rdraw.db_render_control = dsa->db_render_control;
+ /* Enable stream out if needed. */
+ if (rctx->streamout_start) {
+ r600_context_streamout_begin(rctx);
+ rctx->streamout_start = FALSE;
+ }
- /* Emit states. */
+ /* Emit states (the function expects that we emit at most 17 dwords here). */
r600_need_cs_space(rctx, 0, TRUE);
LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
r600_emit_atom(rctx, state);
}
LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
- r600_context_block_emit_dirty(rctx, dirty_block);
- }
- LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
- r600_context_block_resource_emit_dirty(rctx, dirty_block);
+ r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
}
rctx->pm4_dirty_cdwords = 0;
- /* Enable stream out if needed. */
- if (rctx->streamout_start) {
- r600_context_streamout_begin(rctx);
- rctx->streamout_start = FALSE;
- }
-
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_context_draw(rctx, &rdraw);
+ /* draw packet */
+ cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
+ cs->buf[cs->cdw++] = info.instance_count;
+ if (info.indexed) {
+ cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
+ cs->buf[cs->cdw++] = ib.index_size == 4 ?
+ (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
+ (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
+
+ va = r600_resource_va(ctx->screen, ib.buffer);
+ va += ib.offset;
+ cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
+ cs->buf[cs->cdw++] = va;
+ cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
+ cs->buf[cs->cdw++] = info.count;
+ cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
+ cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
+ cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
} else {
- r600_context_draw(rctx, &rdraw);
+ if (info.count_from_stream_output) {
+ struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
+ uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->filled_size);
+
+ r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
+
+ cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
+ cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
+ cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
+ cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
+ cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
+ cs->buf[cs->cdw++] = 0; /* unused */
+
+ cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+ cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->filled_size, RADEON_USAGE_READ);
+ }
+
+ cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
+ cs->buf[cs->cdw++] = info.count;
+ cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
+ (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
}
rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
- if (rctx->framebuffer.zsbuf)
- {
- struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
- ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
+ /* Set the depth buffer as dirty. */
+ if (rctx->framebuffer.zsbuf) {
+ struct pipe_surface *surf = rctx->framebuffer.zsbuf;
+ struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture;
+
+ rtex->dirty_db_mask |= 1 << surf->u.tex.level;
}
pipe_resource_reference(&ib.buffer, NULL);
- u_vbuf_draw_end(rctx->vbuf_mgr);
}
-void _r600_pipe_state_add_reg(struct r600_context *ctx,
- struct r600_pipe_state *state,
- uint32_t offset, uint32_t value,
- uint32_t range_id, uint32_t block_id,
- struct r600_resource *bo,
- enum radeon_bo_usage usage)
+void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
+ struct r600_pipe_state *state,
+ uint32_t offset, uint32_t value,
+ uint32_t range_id, uint32_t block_id,
+ struct r600_resource *bo,
+ enum radeon_bo_usage usage)
+
{
struct r600_range *range;
struct r600_block *block;
assert(state->nregs < R600_BLOCK_MAX_REG);
}
+void _r600_pipe_state_add_reg(struct r600_context *ctx,
+ struct r600_pipe_state *state,
+ uint32_t offset, uint32_t value,
+ uint32_t range_id, uint32_t block_id)
+{
+ _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
+ range_id, block_id, NULL, 0);
+}
+
void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
uint32_t offset, uint32_t value,
struct r600_resource *bo,
projects / mesa.git / blobdiff