nouveau: Add support for SV_WORK_DIM

[mesa.git] / src / gallium / drivers / r600 / r600_state_common.c

diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index eed46b0922daee01b871e454dda1929b7c9a7f89..4b282d0bc9ba378d1fda6713a6431238dee1a4b1 100644 (file)
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -350,9 +350,11 @@ static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 
        if (rs->offset_enable &&
            (rs->offset_units != rctx->poly_offset_state.offset_units ||
-            rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
+            rs->offset_scale != rctx->poly_offset_state.offset_scale ||
+            rs->offset_units_unscaled != rctx->poly_offset_state.offset_units_unscaled)) {
                rctx->poly_offset_state.offset_units = rs->offset_units;
                rctx->poly_offset_state.offset_scale = rs->offset_scale;
+               rctx->poly_offset_state.offset_units_unscaled = rs->offset_units_unscaled;
                r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
        }
 
@@ -512,7 +514,7 @@ static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
 {
        struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
-       pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
+       r600_resource_reference(&shader->buffer, NULL);
        FREE(shader);
 }
 
@@ -533,7 +535,6 @@ static void r600_set_index_buffer(struct pipe_context *ctx,
 void r600_vertex_buffers_dirty(struct r600_context *rctx)
 {
        if (rctx->vertex_buffer_state.dirty_mask) {
-               rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
                rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
                                               util_bitcount(rctx->vertex_buffer_state.dirty_mask);
                r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
@@ -590,7 +591,6 @@ void r600_sampler_views_dirty(struct r600_context *rctx,
                              struct r600_samplerview_state *state)
 {
        if (state->dirty_mask) {
-               rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
                state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
                                     util_bitcount(state->dirty_mask);
                r600_mark_atom_dirty(rctx, &state->atom);
@@ -1048,7 +1048,6 @@ static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
 {
        if (state->dirty_mask) {
-               rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
                state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
                                                                   : util_bitcount(state->dirty_mask)*19;
                r600_mark_atom_dirty(rctx, &state->atom);
@@ -1056,7 +1055,7 @@ void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf
 }
 
 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
-                                    struct pipe_constant_buffer *input)
+                                    const struct pipe_constant_buffer *input)
 {
        struct r600_context *rctx = (struct r600_context *)ctx;
        struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
@@ -1681,7 +1680,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
        }
 
        /* make sure that the gfx ring is only one active */
-       if (rctx->b.dma.cs && rctx->b.dma.cs->cdw) {
+       if (radeon_emitted(rctx->b.dma.cs, 0)) {
                rctx->b.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
        }
 
@@ -1907,8 +1906,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
                        radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit));
                        radeon_emit(cs, info.count);
                        radeon_emit(cs, V_0287F0_DI_SRC_SEL_IMMEDIATE);
-                       memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
-                       cs->cdw += size_dw;
+                       radeon_emit_array(cs, ib.user_buffer, size_dw);
                } else {
                        uint64_t va = r600_resource(ib.buffer)->gpu_address + ib.offset;