#include "r600_pipe.h"
#include "r600d.h"
-static void r600_spi_update(struct r600_pipe_context *rctx);
-
static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
{
static const int prim_conv[] = {
/* common state between evergreen and r600 */
void r600_bind_blend_state(struct pipe_context *ctx, void *state)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
struct r600_pipe_state *rstate;
rstate = &blend->rstate;
rctx->states[rstate->id] = rstate;
rctx->cb_target_mask = blend->cb_target_mask;
- r600_context_pipe_state_set(&rctx->ctx, rstate);
+
+ /* Replace every bit except MULTIWRITE_ENABLE. */
+ rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
+ rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
+
+ r600_context_pipe_state_set(rctx, rstate);
+}
+
+static void r600_set_stencil_ref(struct pipe_context *ctx,
+ const struct r600_stencil_ref *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+ if (rstate == NULL)
+ return;
+
+ rstate->id = R600_PIPE_STATE_STENCIL_REF;
+ r600_pipe_state_add_reg(rstate,
+ R_028430_DB_STENCILREFMASK,
+ S_028430_STENCILREF(state->ref_value[0]) |
+ S_028430_STENCILMASK(state->valuemask[0]) |
+ S_028430_STENCILWRITEMASK(state->writemask[0]),
+ NULL, 0);
+ r600_pipe_state_add_reg(rstate,
+ R_028434_DB_STENCILREFMASK_BF,
+ S_028434_STENCILREF_BF(state->ref_value[1]) |
+ S_028434_STENCILMASK_BF(state->valuemask[1]) |
+ S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
+ NULL, 0);
+
+ free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
+ rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
+ r600_context_pipe_state_set(rctx, rstate);
+}
+
+void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
+ const struct pipe_stencil_ref *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
+ struct r600_stencil_ref ref;
+
+ rctx->stencil_ref = *state;
+
+ if (!dsa)
+ return;
+
+ ref.ref_value[0] = state->ref_value[0];
+ ref.ref_value[1] = state->ref_value[1];
+ ref.valuemask[0] = dsa->valuemask[0];
+ ref.valuemask[1] = dsa->valuemask[1];
+ ref.writemask[0] = dsa->writemask[0];
+ ref.writemask[1] = dsa->writemask[1];
+
+ r600_set_stencil_ref(ctx, &ref);
}
void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_dsa *dsa = state;
struct r600_pipe_state *rstate;
+ struct r600_stencil_ref ref;
if (state == NULL)
return;
rctx->states[rstate->id] = rstate;
rctx->alpha_ref = dsa->alpha_ref;
rctx->alpha_ref_dirty = true;
- r600_context_pipe_state_set(&rctx->ctx, rstate);
+ r600_context_pipe_state_set(rctx, rstate);
+
+ ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
+ ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
+ ref.valuemask[0] = dsa->valuemask[0];
+ ref.valuemask[1] = dsa->valuemask[1];
+ ref.writemask[0] = dsa->writemask[0];
+ ref.writemask[1] = dsa->writemask[1];
+
+ r600_set_stencil_ref(ctx, &ref);
}
void r600_bind_rs_state(struct pipe_context *ctx, void *state)
{
struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
if (state == NULL)
return;
- rctx->clamp_vertex_color = rs->clamp_vertex_color;
- rctx->clamp_fragment_color = rs->clamp_fragment_color;
- rctx->flatshade = rs->flatshade;
rctx->sprite_coord_enable = rs->sprite_coord_enable;
+ rctx->two_side = rs->two_side;
+ rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
+ rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
+ rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
+
rctx->rasterizer = rs;
rctx->states[rs->rstate.id] = &rs->rstate;
- r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
+ r600_context_pipe_state_set(rctx, &rs->rstate);
if (rctx->chip_class >= EVERGREEN) {
evergreen_polygon_offset_update(rctx);
} else {
r600_polygon_offset_update(rctx);
}
- if (rctx->ps_shader && rctx->vs_shader)
- rctx->spi_dirty = true;
}
void r600_delete_rs_state(struct pipe_context *ctx, void *state)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
if (rctx->rasterizer == rs) {
void r600_delete_state(struct pipe_context *ctx, void *state)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
if (rctx->states[rstate->id] == rstate) {
void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_vertex_element *v = (struct r600_vertex_element*)state;
rctx->vertex_elements = v;
v->vmgr_elements);
rctx->states[v->rstate.id] = &v->rstate;
- r600_context_pipe_state_set(&rctx->ctx, &v->rstate);
+ r600_context_pipe_state_set(rctx, &v->rstate);
}
}
void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_vertex_element *v = (struct r600_vertex_element*)state;
if (rctx->states[v->rstate.id] == &v->rstate) {
void r600_set_index_buffer(struct pipe_context *ctx,
const struct pipe_index_buffer *ib)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-
- if (ib) {
- pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
- memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
- } else {
- pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
- memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
- }
+ struct r600_context *rctx = (struct r600_context *)ctx;
- /* TODO make this more like a state */
+ u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
}
void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
const struct pipe_vertex_buffer *buffers)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
int i;
/* Zero states. */
for (i = 0; i < count; i++) {
if (!buffers[i].buffer) {
if (rctx->chip_class >= EVERGREEN) {
- evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
+ evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
} else {
- r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
+ r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
}
}
}
for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
if (rctx->chip_class >= EVERGREEN) {
- evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
+ evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
} else {
- r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
+ r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
}
}
unsigned count,
const struct pipe_vertex_element *elements)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
assert(count < 32);
void *r600_create_shader_state(struct pipe_context *ctx,
const struct pipe_shader_state *state)
{
- struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
+ struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
int r;
shader->tokens = tgsi_dup_tokens(state->tokens);
+ shader->so = state->stream_output;
r = r600_pipe_shader_create(ctx, shader);
if (r) {
void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
/* TODO delete old shader */
rctx->ps_shader = (struct r600_pipe_shader *)state;
if (state) {
- r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
+ r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
+
+ rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
+ rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
}
if (rctx->ps_shader && rctx->vs_shader) {
- rctx->spi_dirty = true;
r600_adjust_gprs(rctx);
}
}
void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
/* TODO delete old shader */
rctx->vs_shader = (struct r600_pipe_shader *)state;
if (state) {
- r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_shader->rstate);
+ r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
}
if (rctx->ps_shader && rctx->vs_shader) {
- rctx->spi_dirty = true;
r600_adjust_gprs(rctx);
}
}
void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
if (rctx->ps_shader == shader) {
void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
if (rctx->vs_shader == shader) {
free(shader);
}
-static void r600_update_alpha_ref(struct r600_pipe_context *rctx)
+static void r600_update_alpha_ref(struct r600_context *rctx)
{
unsigned alpha_ref;
struct r600_pipe_state rstate;
rstate.nregs = 0;
if (rctx->export_16bpc)
alpha_ref &= ~0x1FFF;
- r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL, 0);
+ r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
- r600_context_pipe_state_set(&rctx->ctx, &rstate);
+ r600_context_pipe_state_set(rctx, &rstate);
rctx->alpha_ref_dirty = false;
}
-/* FIXME optimize away spi update when it's not needed */
-static void r600_spi_block_init(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate)
-{
- int i;
- rstate->nregs = 0;
- rstate->id = R600_PIPE_STATE_SPI;
- for (i = 0; i < 32; i++) {
- r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, 0, 0xFFFFFFFF, NULL, 0);
- }
-}
-
-static void r600_spi_update(struct r600_pipe_context *rctx)
-{
- struct r600_pipe_shader *shader = rctx->ps_shader;
- struct r600_pipe_state *rstate = &rctx->spi;
- struct r600_shader *rshader = &shader->shader;
- unsigned i, tmp, sid;
-
- if (rctx->spi.id == 0)
- r600_spi_block_init(rctx, &rctx->spi);
-
- rstate->nregs = 0;
- for (i = 0; i < rshader->ninput; i++) {
-
- sid = rshader->input[i].spi_sid;
-
- if (!sid && (rctx->chip_class >= EVERGREEN))
- continue;
-
- tmp = S_028644_SEMANTIC(sid);
-
- if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
- rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
- rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
- tmp |= S_028644_FLAT_SHADE(rctx->flatshade);
- }
-
- if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
- rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
- tmp |= S_028644_PT_SPRITE_TEX(1);
- }
-
- if (rctx->chip_class < EVERGREEN) {
- if (rshader->input[i].centroid)
- tmp |= S_028644_SEL_CENTROID(1);
-
- if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
- tmp |= S_028644_SEL_LINEAR(1);
- }
-
- r600_pipe_state_mod_reg(rstate, tmp);
- }
-
- rctx->spi_dirty = false;
- r600_context_pipe_state_set(&rctx->ctx, rstate);
-}
-
void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
struct pipe_resource *buffer)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_resource *rbuffer = r600_resource(buffer);
struct r600_pipe_resource_state *rstate;
+ uint64_t va_offset;
uint32_t offset;
/* Note that the state tracker can unbind constant buffers by
}
r600_upload_const_buffer(rctx, &rbuffer, &offset);
+ va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
+ va_offset += offset;
+ va_offset >>= 8;
switch (shader) {
case PIPE_SHADER_VERTEX:
rctx->vs_const_buffer.nregs = 0;
r600_pipe_state_add_reg(&rctx->vs_const_buffer,
- R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
+ R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
ALIGN_DIVUP(buffer->width0 >> 4, 16),
- 0xFFFFFFFF, NULL, 0);
+ NULL, 0);
r600_pipe_state_add_reg(&rctx->vs_const_buffer,
- R_028980_ALU_CONST_CACHE_VS_0,
- offset >> 8, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
- r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
+ R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
+ va_offset, rbuffer, RADEON_USAGE_READ);
+ r600_context_pipe_state_set(rctx, &rctx->vs_const_buffer);
rstate = &rctx->vs_const_buffer_resource[index];
if (!rstate->id) {
}
if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
- evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
+ evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
+ evergreen_context_pipe_state_set_vs_resource(rctx, rstate, index);
} else {
r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
- r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
+ r600_context_pipe_state_set_vs_resource(rctx, rstate, index);
}
break;
case PIPE_SHADER_FRAGMENT:
r600_pipe_state_add_reg(&rctx->ps_const_buffer,
R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
ALIGN_DIVUP(buffer->width0 >> 4, 16),
- 0xFFFFFFFF, NULL, 0);
+ NULL, 0);
r600_pipe_state_add_reg(&rctx->ps_const_buffer,
R_028940_ALU_CONST_CACHE_PS_0,
- offset >> 8, 0xFFFFFFFF, rbuffer, RADEON_USAGE_READ);
- r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
+ va_offset, rbuffer, RADEON_USAGE_READ);
+ r600_context_pipe_state_set(rctx, &rctx->ps_const_buffer);
rstate = &rctx->ps_const_buffer_resource[index];
if (!rstate->id) {
}
}
if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
- evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
+ evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
+ evergreen_context_pipe_state_set_ps_resource(rctx, rstate, index);
} else {
r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
- r600_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
+ r600_context_pipe_state_set_ps_resource(rctx, rstate, index);
}
break;
default:
pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
}
-static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
+struct pipe_stream_output_target *
+r600_create_so_target(struct pipe_context *ctx,
+ struct pipe_resource *buffer,
+ unsigned buffer_offset,
+ unsigned buffer_size)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_so_target *t;
+ void *ptr;
+
+ t = CALLOC_STRUCT(r600_so_target);
+ if (!t) {
+ return NULL;
+ }
+
+ t->b.reference.count = 1;
+ t->b.context = ctx;
+ pipe_resource_reference(&t->b.buffer, buffer);
+ t->b.buffer_offset = buffer_offset;
+ t->b.buffer_size = buffer_size;
+
+ t->filled_size = (struct r600_resource*)
+ pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
+ ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
+ memset(ptr, 0, t->filled_size->buf->size);
+ rctx->ws->buffer_unmap(t->filled_size->buf);
+
+ return &t->b;
+}
+
+void r600_so_target_destroy(struct pipe_context *ctx,
+ struct pipe_stream_output_target *target)
+{
+ struct r600_so_target *t = (struct r600_so_target*)target;
+ pipe_resource_reference(&t->b.buffer, NULL);
+ pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
+ FREE(t);
+}
+
+void r600_set_so_targets(struct pipe_context *ctx,
+ unsigned num_targets,
+ struct pipe_stream_output_target **targets,
+ unsigned append_bitmask)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ unsigned i;
+
+ /* Stop streamout. */
+ if (rctx->num_so_targets) {
+ r600_context_streamout_end(rctx);
+ }
+
+ /* Set the new targets. */
+ for (i = 0; i < num_targets; i++) {
+ pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
+ }
+ for (; i < rctx->num_so_targets; i++) {
+ pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
+ }
+
+ rctx->num_so_targets = num_targets;
+ rctx->streamout_start = num_targets != 0;
+ rctx->streamout_append_bitmask = append_bitmask;
+}
+
+static void r600_vertex_buffer_update(struct r600_context *rctx)
{
struct r600_pipe_resource_state *rstate;
struct r600_resource *rbuffer;
}
if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
- evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
+ evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
+ evergreen_context_pipe_state_set_fs_resource(rctx, rstate, i);
} else {
r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
- r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
+ r600_context_pipe_state_set_fs_resource(rctx, rstate, i);
}
}
}
static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
int r;
r600_pipe_shader_destroy(ctx, shader);
if (r) {
return r;
}
- r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
+ r600_context_pipe_state_set(rctx, &shader->rstate);
return 0;
}
-static void r600_update_derived_state(struct r600_pipe_context *rctx)
+static void r600_update_derived_state(struct r600_context *rctx)
{
+ struct pipe_context * ctx = (struct pipe_context*)rctx;
+ struct r600_pipe_state rstate;
+
+ rstate.nregs = 0;
+
+ if (rstate.nregs)
+ r600_context_pipe_state_set(rctx, &rstate);
+
if (!rctx->blitter->running) {
if (rctx->have_depth_fb || rctx->have_depth_texture)
r600_flush_depth_textures(rctx);
r600_update_sampler_states(rctx);
}
- if (rctx->vs_shader->shader.clamp_color != rctx->clamp_vertex_color) {
- r600_shader_rebuild(&rctx->context, rctx->vs_shader);
- }
-
- if ((rctx->ps_shader->shader.clamp_color != rctx->clamp_fragment_color) ||
+ if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
(rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
r600_shader_rebuild(&rctx->context, rctx->ps_shader);
}
- if (rctx->spi_dirty) {
- r600_spi_update(rctx);
- }
-
if (rctx->alpha_ref_dirty) {
r600_update_alpha_ref(rctx);
}
+
+ if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
+ (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
+ (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
+
+ if (rctx->chip_class >= EVERGREEN)
+ evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
+ else
+ r600_pipe_shader_ps(ctx, rctx->ps_shader);
+
+ r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
+ }
+
}
void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
{
- struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
struct pipe_draw_info info = *dinfo;
struct r600_draw rdraw = {};
struct pipe_index_buffer ib = {};
- unsigned prim, mask;
+ unsigned prim, mask, ls_mask = 0;
- if (!info.count ||
- (info.indexed && !rctx->index_buffer.buffer) ||
+ if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
+ (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
!r600_conv_pipe_prim(info.mode, &prim)) {
return;
}
+ if (!rctx->ps_shader || !rctx->vs_shader)
+ return;
+
r600_update_derived_state(rctx);
- u_vbuf_draw_begin(rctx->vbuf_mgr, dinfo);
+ u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
r600_vertex_buffer_update(rctx);
rdraw.vgt_num_indices = info.count;
rdraw.vgt_num_instances = info.instance_count;
if (info.indexed) {
- /* Adjust min/max_index by the index bias. */
- if (info.max_index != ~0) {
- info.min_index += info.index_bias;
- info.max_index += info.index_bias;
- }
-
/* Initialize the index buffer struct. */
- pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
- ib.index_size = rctx->index_buffer.index_size;
- ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
+ pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
+ ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
+ ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
/* Translate or upload, if needed. */
r600_translate_index_buffer(rctx, &ib, info.count);
} else {
info.index_bias = info.start;
rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
+ if (info.count_from_stream_output) {
+ rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
+
+ r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
+ }
}
+ rctx->vs_so_stride_in_dw = rctx->vs_shader->so.stride;
+
mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
rctx->vgt.id = R600_PIPE_STATE_VGT;
rctx->vgt.nregs = 0;
- r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, info.max_index, 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, info.min_index, 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, 0xFFFFFFFF, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL,
- 0,
- S_028814_PROVOKING_VTX_LAST(1), NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, NULL, 0);
+ if (rctx->chip_class <= R700)
+ r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
}
rctx->vgt.nregs = 0;
r600_pipe_state_mod_reg(&rctx->vgt, prim);
r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
- r600_pipe_state_mod_reg(&rctx->vgt, info.max_index);
- r600_pipe_state_mod_reg(&rctx->vgt, info.min_index);
+ r600_pipe_state_mod_reg(&rctx->vgt, ~0);
+ r600_pipe_state_mod_reg(&rctx->vgt, 0);
r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
r600_pipe_state_mod_reg(&rctx->vgt, 0);
r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
+
+ if (prim == V_008958_DI_PT_LINELIST)
+ ls_mask = 1;
+ else if (prim == V_008958_DI_PT_LINESTRIP)
+ ls_mask = 2;
+ r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
+
if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
- r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1));
+ r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
+ } else {
+ r600_pipe_state_mod_reg(&rctx->vgt, rctx->pa_su_sc_mode_cntl);
}
+ if (rctx->chip_class <= R700)
+ r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
+ r600_pipe_state_mod_reg(&rctx->vgt,
+ rctx->vs_shader->pa_cl_vs_out_cntl |
+ (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
+ r600_pipe_state_mod_reg(&rctx->vgt,
+ rctx->pa_cl_clip_cntl |
+ (rctx->vs_shader->shader.clip_dist_write ||
+ rctx->vs_shader->shader.vs_prohibit_ucps ?
+ 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
+
+ r600_context_pipe_state_set(rctx, &rctx->vgt);
- r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt);
+ rdraw.db_render_override = dsa->db_render_override;
+ rdraw.db_render_control = dsa->db_render_control;
if (rctx->chip_class >= EVERGREEN) {
- evergreen_context_draw(&rctx->ctx, &rdraw);
+ evergreen_context_draw(rctx, &rdraw);
} else {
- r600_context_draw(&rctx->ctx, &rdraw);
+ r600_context_draw(rctx, &rdraw);
}
if (rctx->framebuffer.zsbuf)
void _r600_pipe_state_add_reg(struct r600_context *ctx,
struct r600_pipe_state *state,
- u32 offset, u32 value, u32 mask,
- u32 range_id, u32 block_id,
+ uint32_t offset, uint32_t value,
+ uint32_t range_id, uint32_t block_id,
struct r600_resource *bo,
enum radeon_bo_usage usage)
{
state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
state->regs[state->nregs].value = value;
- state->regs[state->nregs].mask = mask;
state->regs[state->nregs].bo = bo;
state->regs[state->nregs].bo_usage = usage;
}
void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
- u32 offset, u32 value, u32 mask,
+ uint32_t offset, uint32_t value,
struct r600_resource *bo,
enum radeon_bo_usage usage)
{
state->regs[state->nregs].id = offset;
state->regs[state->nregs].block = NULL;
state->regs[state->nregs].value = value;
- state->regs[state->nregs].mask = mask;
state->regs[state->nregs].bo = bo;
state->regs[state->nregs].bo_usage = usage;
projects / mesa.git / blobdiff