* Authors: Dave Airlie <airlied@redhat.com>
* Jerome Glisse <jglisse@redhat.com>
*/
-#include "util/u_blitter.h"
-#include "util/u_memory.h"
-#include "util/u_format.h"
-#include "pipebuffer/pb_buffer.h"
-#include "pipe/p_shader_tokens.h"
-#include "tgsi/tgsi_parse.h"
#include "r600_formats.h"
-#include "r600_pipe.h"
#include "r600d.h"
-#include "r600_hw_context_priv.h"
+
+#include "util/u_blitter.h"
+#include "util/u_upload_mgr.h"
+#include "tgsi/tgsi_parse.h"
+#include <byteswap.h>
static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
{
static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->cs;
- struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom;
+ struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
void r600_init_common_atoms(struct r600_context *rctx)
{
- r600_init_atom(&rctx->atom_surface_sync.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
- r600_init_atom(&rctx->atom_r6xx_flush_and_inv, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
+ r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
+ r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
}
unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
- r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
+ rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
+ r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
}
static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
rstate = &blend->rstate;
rctx->states[rstate->id] = rstate;
rctx->cb_target_mask = blend->cb_target_mask;
-
/* Replace every bit except MULTIWRITE_ENABLE. */
rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
-
+ rctx->dual_src_blend = blend->dual_src_blend;
r600_context_pipe_state_set(rctx, rstate);
}
r600_set_stencil_ref(ctx, &ref);
- if (rctx->atom_db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
- rctx->atom_db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
- r600_atom_dirty(rctx, &rctx->atom_db_misc_state.atom);
+ if (rctx->db_misc_state.flush_depthstencil_enabled != dsa->is_flush) {
+ rctx->db_misc_state.flush_depthstencil_enabled = dsa->is_flush;
+ r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
}
}
+void r600_set_max_scissor(struct r600_context *rctx)
+{
+ /* Set a scissor state such that it doesn't do anything. */
+ struct pipe_scissor_state scissor;
+ scissor.minx = 0;
+ scissor.miny = 0;
+ scissor.maxx = 8192;
+ scissor.maxy = 8192;
+
+ r600_set_scissor_state(rctx, &scissor);
+}
+
void r600_bind_rs_state(struct pipe_context *ctx, void *state)
{
struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
} else {
r600_polygon_offset_update(rctx);
}
+
+ /* Workaround for a missing scissor enable on r600. */
+ if (rctx->chip_class == R600) {
+ if (rs->scissor_enable != rctx->scissor_enable) {
+ rctx->scissor_enable = rs->scissor_enable;
+
+ if (rs->scissor_enable) {
+ r600_set_scissor_state(rctx, &rctx->scissor_state);
+ } else {
+ r600_set_max_scissor(rctx);
+ }
+ }
+ }
}
void r600_delete_rs_state(struct pipe_context *ctx, void *state)
const struct pipe_vertex_buffer *buffers)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- int i;
-
- /* Zero states. */
- for (i = 0; i < count; i++) {
- if (!buffers[i].buffer) {
- r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
- }
- }
- for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
- r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
- }
u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
+ rctx->vertex_buffers_dirty = true;
}
void *r600_create_vertex_elements(struct pipe_context *ctx,
{
struct r600_context *rctx = (struct r600_context *)ctx;
- /* TODO delete old shader */
+ if (!state) {
+ state = rctx->dummy_pixel_shader;
+ }
+
rctx->ps_shader = (struct r600_pipe_shader *)state;
- if (state) {
- r600_inval_shader_cache(rctx);
- r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
- rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
- rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
- }
+ r600_inval_shader_cache(rctx);
+ r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
+
+ rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
+ rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
+
if (rctx->ps_shader && rctx->vs_shader) {
r600_adjust_gprs(rctx);
}
{
struct r600_context *rctx = (struct r600_context *)ctx;
- /* TODO delete old shader */
rctx->vs_shader = (struct r600_pipe_shader *)state;
if (state) {
r600_inval_shader_cache(rctx);
rctx->alpha_ref_dirty = false;
}
+void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
+{
+ r600_inval_shader_cache(rctx);
+ state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
+ : util_bitcount(state->dirty_mask)*19;
+ r600_atom_dirty(rctx, &state->atom);
+}
+
void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
struct pipe_resource *buffer)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_resource *rbuffer = r600_resource(buffer);
- struct r600_pipe_resource_state *rstate;
- uint64_t va_offset;
- uint32_t offset;
+ struct r600_constbuf_state *state;
+ struct r600_constant_buffer *cb;
+ uint8_t *ptr;
+
+ switch (shader) {
+ case PIPE_SHADER_VERTEX:
+ state = &rctx->vs_constbuf_state;
+ break;
+ case PIPE_SHADER_FRAGMENT:
+ state = &rctx->ps_constbuf_state;
+ break;
+ default:
+ return;
+ }
/* Note that the state tracker can unbind constant buffers by
* passing NULL here.
*/
- if (buffer == NULL) {
+ if (unlikely(!buffer)) {
+ state->enabled_mask &= ~(1 << index);
+ state->dirty_mask &= ~(1 << index);
+ pipe_resource_reference(&state->cb[index].buffer, NULL);
return;
}
- r600_inval_shader_cache(rctx);
+ cb = &state->cb[index];
+ cb->buffer_size = buffer->width0;
- r600_upload_const_buffer(rctx, &rbuffer, &offset);
- va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
- va_offset += offset;
- va_offset >>= 8;
+ ptr = u_vbuf_resource(buffer)->user_ptr;
- switch (shader) {
- case PIPE_SHADER_VERTEX:
- rctx->vs_const_buffer.nregs = 0;
- r600_pipe_state_add_reg(&rctx->vs_const_buffer,
- R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
- ALIGN_DIVUP(buffer->width0 >> 4, 16),
- NULL, 0);
- r600_pipe_state_add_reg(&rctx->vs_const_buffer,
- R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
- va_offset, rbuffer, RADEON_USAGE_READ);
- r600_context_pipe_state_set(rctx, &rctx->vs_const_buffer);
-
- rstate = &rctx->vs_const_buffer_resource[index];
- if (!rstate->id) {
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_init_buffer_resource(rctx, rstate);
- } else {
- r600_pipe_init_buffer_resource(rctx, rstate);
+ if (ptr) {
+ /* Upload the user buffer. */
+ if (R600_BIG_ENDIAN) {
+ uint32_t *tmpPtr;
+ unsigned i, size = buffer->width0;
+
+ if (!(tmpPtr = malloc(size))) {
+ R600_ERR("Failed to allocate BE swap buffer.\n");
+ return;
}
- }
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
- } else {
- r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
- }
- r600_context_pipe_state_set_vs_resource(rctx, rstate, index);
- break;
- case PIPE_SHADER_FRAGMENT:
- rctx->ps_const_buffer.nregs = 0;
- r600_pipe_state_add_reg(&rctx->ps_const_buffer,
- R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
- ALIGN_DIVUP(buffer->width0 >> 4, 16),
- NULL, 0);
- r600_pipe_state_add_reg(&rctx->ps_const_buffer,
- R_028940_ALU_CONST_CACHE_PS_0,
- va_offset, rbuffer, RADEON_USAGE_READ);
- r600_context_pipe_state_set(rctx, &rctx->ps_const_buffer);
-
- rstate = &rctx->ps_const_buffer_resource[index];
- if (!rstate->id) {
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_init_buffer_resource(rctx, rstate);
- } else {
- r600_pipe_init_buffer_resource(rctx, rstate);
+ for (i = 0; i < size / 4; ++i) {
+ tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
}
- }
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
+
+ u_upload_data(rctx->vbuf_mgr->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
+ free(tmpPtr);
} else {
- r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
+ u_upload_data(rctx->vbuf_mgr->uploader, 0, buffer->width0, ptr, &cb->buffer_offset, &cb->buffer);
}
- r600_context_pipe_state_set_ps_resource(rctx, rstate, index);
- break;
- default:
- R600_ERR("unsupported %d\n", shader);
- return;
+ } else {
+ /* Setup the hw buffer. */
+ cb->buffer_offset = 0;
+ pipe_resource_reference(&cb->buffer, buffer);
}
- if (buffer != &rbuffer->b.b.b)
- pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
+ state->enabled_mask |= 1 << index;
+ state->dirty_mask |= 1 << index;
+ r600_constant_buffers_dirty(rctx, state);
}
struct pipe_stream_output_target *
rctx->streamout_append_bitmask = append_bitmask;
}
-static void r600_vertex_buffer_update(struct r600_context *rctx)
-{
- struct r600_pipe_resource_state *rstate;
- struct r600_resource *rbuffer;
- struct pipe_vertex_buffer *vertex_buffer;
- unsigned i, count, offset;
-
- r600_inval_vertex_cache(rctx);
-
- if (rctx->vertex_elements->vbuffer_need_offset) {
- /* one resource per vertex elements */
- count = rctx->vertex_elements->count;
- } else {
- /* bind vertex buffer once */
- count = rctx->vbuf_mgr->nr_real_vertex_buffers;
- }
-
- for (i = 0 ; i < count; i++) {
- rstate = &rctx->fs_resource[i];
-
- if (rctx->vertex_elements->vbuffer_need_offset) {
- /* one resource per vertex elements */
- unsigned vbuffer_index;
- vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
- vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
- rbuffer = (struct r600_resource*)vertex_buffer->buffer;
- offset = rctx->vertex_elements->vbuffer_offset[i];
- } else {
- /* bind vertex buffer once */
- vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
- rbuffer = (struct r600_resource*)vertex_buffer->buffer;
- offset = 0;
- }
- if (vertex_buffer == NULL || rbuffer == NULL)
- continue;
- offset += vertex_buffer->buffer_offset;
-
- if (!rstate->id) {
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_init_buffer_resource(rctx, rstate);
- } else {
- r600_pipe_init_buffer_resource(rctx, rstate);
- }
- }
-
- if (rctx->chip_class >= EVERGREEN) {
- evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
- } else {
- r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
- }
- r600_context_pipe_state_set_fs_resource(rctx, rstate, i);
- }
-}
-
static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
{
struct r600_context *rctx = (struct r600_context *)ctx;
static void r600_update_derived_state(struct r600_context *rctx)
{
struct pipe_context * ctx = (struct pipe_context*)rctx;
- struct r600_pipe_state rstate;
-
- rstate.nregs = 0;
-
- if (rstate.nregs)
- r600_context_pipe_state_set(rctx, &rstate);
if (!rctx->blitter->running) {
if (rctx->have_depth_fb || rctx->have_depth_texture)
r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
}
+ if (rctx->dual_src_blend)
+ rctx->cb_shader_mask = rctx->ps_shader->ps_cb_shader_mask | rctx->fb_cb_shader_mask;
+ else
+ rctx->cb_shader_mask = rctx->fb_cb_shader_mask;
+}
+
+static unsigned r600_conv_prim_to_gs_out(unsigned mode)
+{
+ static const int prim_conv[] = {
+ V_028A6C_OUTPRIM_TYPE_POINTLIST,
+ V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP
+ };
+ assert(mode < Elements(prim_conv));
+
+ return prim_conv[mode];
}
void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
struct r600_atom *state = NULL, *next_state = NULL;
struct radeon_winsys_cs *cs = rctx->cs;
uint64_t va;
+ uint8_t *ptr;
if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
(info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
!r600_conv_pipe_prim(info.mode, &prim)) {
+ assert(0);
return;
}
- if (!rctx->ps_shader || !rctx->vs_shader)
+ if (!rctx->vs_shader) {
+ assert(0);
return;
+ }
r600_update_derived_state(rctx);
- u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
- r600_vertex_buffer_update(rctx);
+ /* Update vertex buffers. */
+ if ((u_vbuf_draw_begin(rctx->vbuf_mgr, &info) & U_VBUF_BUFFERS_UPDATED) ||
+ rctx->vertex_buffers_dirty) {
+ r600_inval_vertex_cache(rctx);
+ rctx->vertex_buffer_state.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 10) *
+ rctx->vbuf_mgr->nr_real_vertex_buffers;
+ r600_atom_dirty(rctx, &rctx->vertex_buffer_state);
+ rctx->vertex_buffers_dirty = FALSE;
+ }
if (info.indexed) {
/* Initialize the index buffer struct. */
/* Translate or upload, if needed. */
r600_translate_index_buffer(rctx, &ib, info.count);
- if (u_vbuf_resource(ib.buffer)->user_ptr) {
- r600_upload_index_buffer(rctx, &ib, info.count);
+ ptr = u_vbuf_resource(ib.buffer)->user_ptr;
+ if (ptr) {
+ u_upload_data(rctx->vbuf_mgr->uploader, 0, info.count * ib.index_size,
+ ptr, &ib.offset, &ib.buffer);
}
} else {
info.index_bias = info.start;
rctx->vgt.id = R600_PIPE_STATE_VGT;
rctx->vgt.nregs = 0;
r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
+
+ if (rctx->chip_class <= R700)
+ r600_pipe_state_add_reg(&rctx->vgt, R_0280A4_CB_COLOR1_INFO, 0, NULL, 0);
+ else
+ r600_pipe_state_add_reg(&rctx->vgt, 0x28CAC, 0, NULL, 0);
}
rctx->vgt.nregs = 0;
r600_pipe_state_mod_reg(&rctx->vgt, prim);
+ r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
+ r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_shader_mask);
r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
rctx->vs_shader->shader.vs_prohibit_ucps ?
0 : rctx->rasterizer->clip_plane_enable & 0x3F));
+ if (rctx->dual_src_blend) {
+ r600_pipe_state_mod_reg(&rctx->vgt,
+ rctx->color0_format);
+ }
+
r600_context_pipe_state_set(rctx, &rctx->vgt);
/* Emit states (the function expects that we emit at most 17 dwords here). */
projects / mesa.git / blobdiff