return;
rstate->id = R600_PIPE_STATE_BLEND_COLOR;
- r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
- r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
+ r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
+ r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
+ r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
+ r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
R_028430_DB_STENCILREFMASK,
S_028430_STENCILREF(state->ref_value[0]) |
S_028430_STENCILMASK(state->valuemask[0]) |
- S_028430_STENCILWRITEMASK(state->writemask[0]),
- NULL, 0);
+ S_028430_STENCILWRITEMASK(state->writemask[0]));
r600_pipe_state_add_reg(rstate,
R_028434_DB_STENCILREFMASK_BF,
S_028434_STENCILREF_BF(state->ref_value[1]) |
S_028434_STENCILMASK_BF(state->valuemask[1]) |
- S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
- NULL, 0);
+ S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
rctx->vertex_elements = v;
if (v) {
r600_inval_shader_cache(rctx);
- u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
- v->vmgr_elements);
rctx->states[v->rstate.id] = &v->rstate;
r600_context_pipe_state_set(rctx, &v->rstate);
rctx->vertex_elements = NULL;
pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
- u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
FREE(state);
}
-
void r600_set_index_buffer(struct pipe_context *ctx,
const struct pipe_index_buffer *ib)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
+ if (ib) {
+ pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
+ memcpy(&rctx->index_buffer, ib, sizeof(*ib));
+ } else {
+ pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
+ }
}
void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
{
struct r600_context *rctx = (struct r600_context *)ctx;
- u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
- rctx->vertex_buffers_dirty = true;
+ util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count);
+
+ r600_inval_vertex_cache(rctx);
+ rctx->vertex_buffer_state.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 10) *
+ rctx->nr_vertex_buffers;
+ r600_atom_dirty(rctx, &rctx->vertex_buffer_state);
}
void *r600_create_vertex_elements(struct pipe_context *ctx,
return NULL;
v->count = count;
- v->vmgr_elements =
- u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
- elements, v->elements);
+ memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
FREE(v);
rstate.nregs = 0;
if (rctx->export_16bpc)
alpha_ref &= ~0x1FFF;
- r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
+ r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
r600_context_pipe_state_set(rctx, &rstate);
rctx->alpha_ref_dirty = false;
}
void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
- struct pipe_resource *buffer)
+ struct pipe_constant_buffer *input)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_constbuf_state *state;
- struct r600_constant_buffer *cb;
+ struct pipe_constant_buffer *cb;
uint8_t *ptr;
switch (shader) {
/* Note that the state tracker can unbind constant buffers by
* passing NULL here.
*/
- if (unlikely(!buffer)) {
+ if (unlikely(!input)) {
state->enabled_mask &= ~(1 << index);
state->dirty_mask &= ~(1 << index);
pipe_resource_reference(&state->cb[index].buffer, NULL);
}
cb = &state->cb[index];
- cb->buffer_size = buffer->width0;
+ cb->buffer_size = input->buffer_size;
- ptr = u_vbuf_resource(buffer)->user_ptr;
+ ptr = input->buffer->user_ptr;
if (ptr) {
/* Upload the user buffer. */
if (R600_BIG_ENDIAN) {
uint32_t *tmpPtr;
- unsigned i, size = buffer->width0;
+ unsigned i, size = input->buffer_size;
if (!(tmpPtr = malloc(size))) {
R600_ERR("Failed to allocate BE swap buffer.\n");
tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
}
- u_upload_data(rctx->vbuf_mgr->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
+ u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
free(tmpPtr);
} else {
- u_upload_data(rctx->vbuf_mgr->uploader, 0, buffer->width0, ptr, &cb->buffer_offset, &cb->buffer);
+ u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
}
} else {
/* Setup the hw buffer. */
- cb->buffer_offset = 0;
- pipe_resource_reference(&cb->buffer, buffer);
+ cb->buffer_offset = input->buffer_offset;
+ pipe_resource_reference(&cb->buffer, input->buffer);
}
state->enabled_mask |= 1 << index;
t->filled_size = (struct r600_resource*)
pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
- ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
+ ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
memset(ptr, 0, t->filled_size->buf->size);
- rctx->ws->buffer_unmap(t->filled_size->buf);
+ rctx->ws->buffer_unmap(t->filled_size->cs_buf);
return &t->b;
}
uint8_t *ptr;
if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
- (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
+ (info.indexed && !rctx->index_buffer.buffer) ||
!r600_conv_pipe_prim(info.mode, &prim)) {
assert(0);
return;
r600_update_derived_state(rctx);
- /* Update vertex buffers. */
- if ((u_vbuf_draw_begin(rctx->vbuf_mgr, &info) & U_VBUF_BUFFERS_UPDATED) ||
- rctx->vertex_buffers_dirty) {
- r600_inval_vertex_cache(rctx);
- rctx->vertex_buffer_state.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 10) *
- rctx->vbuf_mgr->nr_real_vertex_buffers;
- r600_atom_dirty(rctx, &rctx->vertex_buffer_state);
- rctx->vertex_buffers_dirty = FALSE;
- }
-
if (info.indexed) {
/* Initialize the index buffer struct. */
- pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
- ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
- ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
+ pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
+ ib.index_size = rctx->index_buffer.index_size;
+ ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
/* Translate or upload, if needed. */
r600_translate_index_buffer(rctx, &ib, info.count);
- ptr = u_vbuf_resource(ib.buffer)->user_ptr;
+ ptr = ib.buffer->user_ptr;
if (ptr) {
- u_upload_data(rctx->vbuf_mgr->uploader, 0, info.count * ib.index_size,
+ u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
ptr, &ib.offset, &ib.buffer);
}
} else {
if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
rctx->vgt.id = R600_PIPE_STATE_VGT;
rctx->vgt.nregs = 0;
- r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask);
+ r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
+ r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
+ r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
if (rctx->chip_class <= R700)
- r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control);
+ r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
if (rctx->chip_class <= R700)
- r600_pipe_state_add_reg(&rctx->vgt, R_0280A4_CB_COLOR1_INFO, 0, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_0280A4_CB_COLOR1_INFO, 0);
else
- r600_pipe_state_add_reg(&rctx->vgt, 0x28CAC, 0, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, 0x28CAC, 0);
}
rctx->vgt.nregs = 0;
}
pipe_resource_reference(&ib.buffer, NULL);
- u_vbuf_draw_end(rctx->vbuf_mgr);
}
-void _r600_pipe_state_add_reg(struct r600_context *ctx,
- struct r600_pipe_state *state,
- uint32_t offset, uint32_t value,
- uint32_t range_id, uint32_t block_id,
- struct r600_resource *bo,
- enum radeon_bo_usage usage)
+void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
+ struct r600_pipe_state *state,
+ uint32_t offset, uint32_t value,
+ uint32_t range_id, uint32_t block_id,
+ struct r600_resource *bo,
+ enum radeon_bo_usage usage)
+
{
struct r600_range *range;
struct r600_block *block;
assert(state->nregs < R600_BLOCK_MAX_REG);
}
+void _r600_pipe_state_add_reg(struct r600_context *ctx,
+ struct r600_pipe_state *state,
+ uint32_t offset, uint32_t value,
+ uint32_t range_id, uint32_t block_id)
+{
+ _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
+ range_id, block_id, NULL, 0);
+}
+
void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
uint32_t offset, uint32_t value,
struct r600_resource *bo,
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