#include "r600_formats.h"
#include "r600d.h"
-#include "util/u_blitter.h"
+#include "util/u_draw_quad.h"
#include "util/u_upload_mgr.h"
#include "tgsi/tgsi_parse.h"
#include <byteswap.h>
+#define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
+
static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->cs;
cs->cdw += cb->atom.num_dw;
}
-void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
+void r600_init_command_buffer(struct r600_context *rctx, struct r600_command_buffer *cb, unsigned id, unsigned num_dw)
{
- cb->atom.emit = r600_emit_command_buffer;
- cb->atom.num_dw = 0;
- cb->atom.flags = flags;
+ r600_init_atom(rctx, &cb->atom, id, r600_emit_command_buffer, 0);
cb->buf = CALLOC(1, 4 * num_dw);
cb->max_num_dw = num_dw;
}
FREE(cb->buf);
}
-static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
-{
- struct radeon_winsys_cs *cs = rctx->cs;
- struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
-
- cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
- cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */
- cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */
- cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */
- cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */
-
- a->flush_flags = 0;
-}
-
-static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
-{
- struct radeon_winsys_cs *cs = rctx->cs;
- cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
- cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
-}
-
-void r600_init_atom(struct r600_atom *atom,
+void r600_init_atom(struct r600_context *rctx,
+ struct r600_atom *atom,
+ unsigned id,
void (*emit)(struct r600_context *ctx, struct r600_atom *state),
- unsigned num_dw, enum r600_atom_flags flags)
+ unsigned num_dw)
{
+ assert(id < R600_NUM_ATOMS);
+ assert(rctx->atoms[id] == NULL);
+ rctx->atoms[id] = atom;
+ atom->id = id;
atom->emit = emit;
atom->num_dw = num_dw;
- atom->flags = flags;
-}
-
-void r600_init_common_atoms(struct r600_context *rctx)
-{
- r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY);
- r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
+ atom->dirty = false;
}
-unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
+void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
{
- unsigned flags = 0;
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
+ unsigned alpha_ref = a->sx_alpha_ref;
- if (rctx->framebuffer.nr_cbufs) {
- flags |= S_0085F0_CB_ACTION_ENA(1) |
- (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
+ if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
+ alpha_ref &= ~0x1FFF;
}
- /* Workaround for broken flushing on some R6xx chipsets. */
- if (rctx->family == CHIP_RV670 ||
- rctx->family == CHIP_RS780 ||
- rctx->family == CHIP_RS880) {
- flags |= S_0085F0_CB1_DEST_BASE_ENA(1) |
- S_0085F0_DEST_BASE_0_ENA(1);
- }
- return flags;
+ r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
+ a->sx_alpha_test_control |
+ S_028410_ALPHA_TEST_BYPASS(a->bypass));
+ r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
}
-void r600_texture_barrier(struct pipe_context *ctx)
+static void r600_texture_barrier(struct pipe_context *ctx)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
- r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
+ rctx->flags |= R600_CONTEXT_CB_FLUSH | R600_CONTEXT_TEX_FLUSH;
+
+ /* R6xx errata */
+ if (rctx->chip_class == R600) {
+ rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
+ }
}
static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
-1,
-1,
-1,
- -1
+ -1,
+ V_008958_DI_PT_RECTLIST
};
*prim = prim_conv[pprim];
}
/* common state between evergreen and r600 */
-void r600_bind_blend_state(struct pipe_context *ctx, void *state)
+
+static void r600_bind_blend_state_internal(struct r600_context *rctx,
+ struct r600_pipe_blend *blend)
{
- struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
struct r600_pipe_state *rstate;
bool update_cb = false;
- if (state == NULL)
- return;
rstate = &blend->rstate;
rctx->states[rstate->id] = rstate;
- rctx->dual_src_blend = blend->dual_src_blend;
r600_context_pipe_state_set(rctx, rstate);
if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
}
}
-void r600_set_blend_color(struct pipe_context *ctx,
- const struct pipe_blend_color *state)
+static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+ struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
- if (rstate == NULL)
+ if (blend == NULL)
return;
- rstate->id = R600_PIPE_STATE_BLEND_COLOR;
- r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
- r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
- r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
- r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
+ rctx->blend = blend;
+ rctx->alpha_to_one = blend->alpha_to_one;
+ rctx->dual_src_blend = blend->dual_src_blend;
- free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
- rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
- r600_context_pipe_state_set(rctx, rstate);
+ if (!rctx->blend_override)
+ r600_bind_blend_state_internal(rctx, blend);
+}
+
+static void r600_set_blend_color(struct pipe_context *ctx,
+ const struct pipe_blend_color *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ rctx->blend_color.state = *state;
+ r600_atom_dirty(rctx, &rctx->blend_color.atom);
+}
+
+void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct pipe_blend_color *state = &rctx->blend_color.state;
+
+ r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
+ r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
+ r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
+ r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
+ r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
+}
+
+static void r600_set_clip_state(struct pipe_context *ctx,
+ const struct pipe_clip_state *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct pipe_constant_buffer cb;
+
+ rctx->clip_state.state = *state;
+ r600_atom_dirty(rctx, &rctx->clip_state.atom);
+
+ cb.buffer = NULL;
+ cb.user_buffer = state->ucp;
+ cb.buffer_offset = 0;
+ cb.buffer_size = 4*4*8;
+ ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
+ pipe_resource_reference(&cb.buffer, NULL);
}
static void r600_set_stencil_ref(struct pipe_context *ctx,
const struct r600_stencil_ref *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- if (rstate == NULL)
- return;
+ rctx->stencil_ref.state = *state;
+ r600_atom_dirty(rctx, &rctx->stencil_ref.atom);
+}
- rstate->id = R600_PIPE_STATE_STENCIL_REF;
- r600_pipe_state_add_reg(rstate,
- R_028430_DB_STENCILREFMASK,
- S_028430_STENCILREF(state->ref_value[0]) |
- S_028430_STENCILMASK(state->valuemask[0]) |
- S_028430_STENCILWRITEMASK(state->writemask[0]));
- r600_pipe_state_add_reg(rstate,
- R_028434_DB_STENCILREFMASK_BF,
- S_028434_STENCILREF_BF(state->ref_value[1]) |
- S_028434_STENCILMASK_BF(state->valuemask[1]) |
- S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
-
- free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
- rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
- r600_context_pipe_state_set(rctx, rstate);
+void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
+
+ r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
+ r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
+ S_028430_STENCILREF(a->state.ref_value[0]) |
+ S_028430_STENCILMASK(a->state.valuemask[0]) |
+ S_028430_STENCILWRITEMASK(a->state.writemask[0]));
+ r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
+ S_028434_STENCILREF_BF(a->state.ref_value[1]) |
+ S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
+ S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
}
-void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
- const struct pipe_stencil_ref *state)
+static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
+ const struct pipe_stencil_ref *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
struct r600_stencil_ref ref;
- rctx->stencil_ref = *state;
+ rctx->stencil_ref.pipe_state = *state;
if (!dsa)
return;
r600_set_stencil_ref(ctx, &ref);
}
-void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
+static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_dsa *dsa = state;
return;
rstate = &dsa->rstate;
rctx->states[rstate->id] = rstate;
- rctx->sx_alpha_test_control &= ~0xff;
- rctx->sx_alpha_test_control |= dsa->sx_alpha_test_control;
- rctx->alpha_ref = dsa->alpha_ref;
- rctx->alpha_ref_dirty = true;
r600_context_pipe_state_set(rctx, rstate);
- ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
- ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
+ ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
+ ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
ref.valuemask[0] = dsa->valuemask[0];
ref.valuemask[1] = dsa->valuemask[1];
ref.writemask[0] = dsa->writemask[0];
ref.writemask[1] = dsa->writemask[1];
r600_set_stencil_ref(ctx, &ref);
+
+ /* Update alphatest state. */
+ if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
+ rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
+ rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
+ rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
+ r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
+ }
}
void r600_set_max_scissor(struct r600_context *rctx)
r600_set_scissor_state(rctx, &scissor);
}
-void r600_bind_rs_state(struct pipe_context *ctx, void *state)
+static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
{
struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
struct r600_context *rctx = (struct r600_context *)ctx;
rctx->two_side = rs->two_side;
rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
+ rctx->multisample_enable = rs->multisample_enable;
rctx->rasterizer = rs;
}
}
-void r600_delete_rs_state(struct pipe_context *ctx, void *state)
+static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
free(rs);
}
-void r600_sampler_view_destroy(struct pipe_context *ctx,
- struct pipe_sampler_view *state)
+static void r600_sampler_view_destroy(struct pipe_context *ctx,
+ struct pipe_sampler_view *state)
{
struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
FREE(resource);
}
-void r600_delete_state(struct pipe_context *ctx, void *state)
+void r600_sampler_states_dirty(struct r600_context *rctx,
+ struct r600_sampler_states *state)
+{
+ if (state->dirty_mask) {
+ if (state->dirty_mask & state->has_bordercolor_mask) {
+ rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
+ }
+ state->atom.num_dw =
+ util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
+ util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
+ r600_atom_dirty(rctx, &state->atom);
+ }
+}
+
+static void r600_bind_sampler_states(struct pipe_context *pipe,
+ unsigned shader,
+ unsigned start,
+ unsigned count, void **states)
+{
+ struct r600_context *rctx = (struct r600_context *)pipe;
+ struct r600_textures_info *dst = &rctx->samplers[shader];
+ struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
+ int seamless_cube_map = -1;
+ unsigned i;
+ /* This sets 1-bit for states with index >= count. */
+ uint32_t disable_mask = ~((1ull << count) - 1);
+ /* These are the new states set by this function. */
+ uint32_t new_mask = 0;
+
+ assert(start == 0); /* XXX fix below */
+
+ for (i = 0; i < count; i++) {
+ struct r600_pipe_sampler_state *rstate = rstates[i];
+
+ if (rstate == dst->states.states[i]) {
+ continue;
+ }
+
+ if (rstate) {
+ if (rstate->border_color_use) {
+ dst->states.has_bordercolor_mask |= 1 << i;
+ } else {
+ dst->states.has_bordercolor_mask &= ~(1 << i);
+ }
+ seamless_cube_map = rstate->seamless_cube_map;
+
+ new_mask |= 1 << i;
+ } else {
+ disable_mask |= 1 << i;
+ }
+ }
+
+ memcpy(dst->states.states, rstates, sizeof(void*) * count);
+ memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
+
+ dst->states.enabled_mask &= ~disable_mask;
+ dst->states.dirty_mask &= dst->states.enabled_mask;
+ dst->states.enabled_mask |= new_mask;
+ dst->states.dirty_mask |= new_mask;
+ dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
+
+ r600_sampler_states_dirty(rctx, &dst->states);
+
+ /* Seamless cubemap state. */
+ if (rctx->chip_class <= R700 &&
+ seamless_cube_map != -1 &&
+ seamless_cube_map != rctx->seamless_cube_map.enabled) {
+ /* change in TA_CNTL_AUX need a pipeline flush */
+ rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
+ rctx->seamless_cube_map.enabled = seamless_cube_map;
+ r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
+ }
+}
+
+static void r600_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
+{
+ r600_bind_sampler_states(ctx, PIPE_SHADER_VERTEX, 0, count, states);
+}
+
+static void r600_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
+{
+ r600_bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 0, count, states);
+}
+
+static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
+{
+ free(state);
+}
+
+static void r600_delete_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
free(rstate);
}
-void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
+static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_vertex_element *v = (struct r600_vertex_element*)state;
rctx->vertex_elements = v;
if (v) {
- r600_inval_shader_cache(rctx);
-
rctx->states[v->rstate.id] = &v->rstate;
r600_context_pipe_state_set(rctx, &v->rstate);
}
}
-void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
+static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_vertex_element *v = (struct r600_vertex_element*)state;
FREE(state);
}
-void r600_set_index_buffer(struct pipe_context *ctx,
+static void r600_set_index_buffer(struct pipe_context *ctx,
const struct pipe_index_buffer *ib)
{
struct r600_context *rctx = (struct r600_context *)ctx;
void r600_vertex_buffers_dirty(struct r600_context *rctx)
{
if (rctx->vertex_buffer_state.dirty_mask) {
- r600_inval_vertex_cache(rctx);
+ rctx->flags |= rctx->has_vertex_cache ? R600_CONTEXT_VTX_FLUSH : R600_CONTEXT_TEX_FLUSH;
rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
util_bitcount(rctx->vertex_buffer_state.dirty_mask);
r600_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
}
}
-void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
+static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
const struct pipe_vertex_buffer *input)
{
struct r600_context *rctx = (struct r600_context *)ctx;
r600_vertex_buffers_dirty(rctx);
}
-void r600_set_sampler_views(struct r600_context *rctx,
- struct r600_textures_info *dst,
- unsigned count,
- struct pipe_sampler_view **views,
- void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
+void r600_sampler_views_dirty(struct r600_context *rctx,
+ struct r600_samplerview_state *state)
{
+ if (state->dirty_mask) {
+ rctx->flags |= R600_CONTEXT_TEX_FLUSH;
+ state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
+ util_bitcount(state->dirty_mask);
+ r600_atom_dirty(rctx, &state->atom);
+ }
+}
+
+static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
+ unsigned start, unsigned count,
+ struct pipe_sampler_view **views)
+{
+ struct r600_context *rctx = (struct r600_context *) pipe;
+ struct r600_textures_info *dst = &rctx->samplers[shader];
struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
+ uint32_t dirty_sampler_states_mask = 0;
unsigned i;
+ /* This sets 1-bit for textures with index >= count. */
+ uint32_t disable_mask = ~((1ull << count) - 1);
+ /* These are the new textures set by this function. */
+ uint32_t new_mask = 0;
+
+ /* Set textures with index >= count to NULL. */
+ uint32_t remaining_mask;
+
+ assert(start == 0); /* XXX fix below */
+
+ remaining_mask = dst->views.enabled_mask & disable_mask;
+
+ while (remaining_mask) {
+ i = u_bit_scan(&remaining_mask);
+ assert(dst->views.views[i]);
- if (count)
- r600_inval_texture_cache(rctx);
+ pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
+ }
for (i = 0; i < count; i++) {
- if (rviews[i] == dst->views[i]) {
+ if (rviews[i] == dst->views.views[i]) {
continue;
}
if (rviews[i]) {
- struct r600_resource_texture *rtex =
- (struct r600_resource_texture*)rviews[i]->base.texture;
+ struct r600_texture *rtex =
+ (struct r600_texture*)rviews[i]->base.texture;
if (rtex->is_depth && !rtex->is_flushing_texture) {
- dst->depth_texture_mask |= 1 << i;
+ dst->views.compressed_depthtex_mask |= 1 << i;
+ } else {
+ dst->views.compressed_depthtex_mask &= ~(1 << i);
+ }
+
+ /* Track compressed colorbuffers for Evergreen (Cayman doesn't need this). */
+ if (rctx->chip_class != CAYMAN && rtex->cmask_size && rtex->fmask_size) {
+ dst->views.compressed_colortex_mask |= 1 << i;
} else {
- dst->depth_texture_mask &= ~(1 << i);
+ dst->views.compressed_colortex_mask &= ~(1 << i);
}
- /* Changing from array to non-arrays textures and vice
- * versa requires updating TEX_ARRAY_OVERRIDE on R6xx-R7xx. */
+ /* Changing from array to non-arrays textures and vice versa requires
+ * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
if (rctx->chip_class <= R700 &&
+ (dst->states.enabled_mask & (1 << i)) &&
(rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
- dst->samplers_dirty = true;
+ dirty_sampler_states_mask |= 1 << i;
}
- set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
+ pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
+ new_mask |= 1 << i;
} else {
- set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
- dst->depth_texture_mask &= ~(1 << i);
+ pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
+ disable_mask |= 1 << i;
}
-
- pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], views[i]);
}
- for (i = count; i < dst->n_views; i++) {
- if (dst->views[i]) {
- set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
- pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
- }
+ dst->views.enabled_mask &= ~disable_mask;
+ dst->views.dirty_mask &= dst->views.enabled_mask;
+ dst->views.enabled_mask |= new_mask;
+ dst->views.dirty_mask |= new_mask;
+ dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
+ dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
+
+ r600_sampler_views_dirty(rctx, &dst->views);
+
+ if (dirty_sampler_states_mask) {
+ dst->states.dirty_mask |= dirty_sampler_states_mask;
+ r600_sampler_states_dirty(rctx, &dst->states);
}
+}
- dst->n_views = count;
+static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
+ struct pipe_sampler_view **views)
+{
+ r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
}
-void *r600_create_vertex_elements(struct pipe_context *ctx,
- unsigned count,
- const struct pipe_vertex_element *elements)
+static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
+ struct pipe_sampler_view **views)
+{
+ r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
+}
+
+static void r600_set_viewport_state(struct pipe_context *ctx,
+ const struct pipe_viewport_state *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+
+ rctx->viewport.state = *state;
+ r600_atom_dirty(rctx, &rctx->viewport.atom);
+}
+
+void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct pipe_viewport_state *state = &rctx->viewport.state;
+
+ r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
+ r600_write_value(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
+ r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
+ r600_write_value(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
+ r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
+ r600_write_value(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
+ r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
+}
+
+static void *r600_create_vertex_elements(struct pipe_context *ctx, unsigned count,
+ const struct pipe_vertex_element *elements)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
if (sel->type == PIPE_SHADER_FRAGMENT) {
key = rctx->two_side |
- MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 1;
+ ((rctx->alpha_to_one && rctx->multisample_enable && !rctx->cb0_is_integer) << 1) |
+ (MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 2);
} else
key = 0;
return sel;
}
-void *r600_create_shader_state_ps(struct pipe_context *ctx,
- const struct pipe_shader_state *state)
+static void *r600_create_ps_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
{
return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
}
-void *r600_create_shader_state_vs(struct pipe_context *ctx,
- const struct pipe_shader_state *state)
+static void *r600_create_vs_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
{
return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
}
-void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
+static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
}
}
-void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
+static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
}
-void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
+static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
r600_delete_shader_selector(ctx, sel);
}
-void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
+static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
r600_delete_shader_selector(ctx, sel);
}
-static void r600_update_alpha_ref(struct r600_context *rctx)
-{
- unsigned alpha_ref;
- struct r600_pipe_state rstate;
-
- alpha_ref = rctx->alpha_ref;
- rstate.nregs = 0;
- if (rctx->export_16bpc && rctx->chip_class >= EVERGREEN) {
- alpha_ref &= ~0x1FFF;
- }
- r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
-
- r600_context_pipe_state_set(rctx, &rstate);
- rctx->alpha_ref_dirty = false;
-}
-
void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
{
if (state->dirty_mask) {
- r600_inval_shader_cache(rctx);
+ rctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
: util_bitcount(state->dirty_mask)*19;
r600_atom_dirty(rctx, &state->atom);
}
}
-void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
- struct pipe_constant_buffer *input)
+static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
+ struct pipe_constant_buffer *input)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_constbuf_state *state;
+ struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
struct pipe_constant_buffer *cb;
const uint8_t *ptr;
- switch (shader) {
- case PIPE_SHADER_VERTEX:
- state = &rctx->vs_constbuf_state;
- break;
- case PIPE_SHADER_FRAGMENT:
- state = &rctx->ps_constbuf_state;
- break;
- default:
- return;
- }
-
/* Note that the state tracker can unbind constant buffers by
* passing NULL here.
*/
r600_constant_buffers_dirty(rctx, state);
}
-struct pipe_stream_output_target *
+static struct pipe_stream_output_target *
r600_create_so_target(struct pipe_context *ctx,
struct pipe_resource *buffer,
unsigned buffer_offset,
return &t->b;
}
-void r600_so_target_destroy(struct pipe_context *ctx,
- struct pipe_stream_output_target *target)
+static void r600_so_target_destroy(struct pipe_context *ctx,
+ struct pipe_stream_output_target *target)
{
struct r600_so_target *t = (struct r600_so_target*)target;
pipe_resource_reference(&t->b.buffer, NULL);
FREE(t);
}
-void r600_set_so_targets(struct pipe_context *ctx,
- unsigned num_targets,
- struct pipe_stream_output_target **targets,
- unsigned append_bitmask)
+static void r600_set_so_targets(struct pipe_context *ctx,
+ unsigned num_targets,
+ struct pipe_stream_output_target **targets,
+ unsigned append_bitmask)
{
struct r600_context *rctx = (struct r600_context *)ctx;
unsigned i;
rctx->streamout_append_bitmask = append_bitmask;
}
+static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
+{
+ struct r600_context *rctx = (struct r600_context*)pipe;
+
+ if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
+ return;
+
+ rctx->sample_mask.sample_mask = sample_mask;
+ r600_atom_dirty(rctx, &rctx->sample_mask.atom);
+}
+
static void r600_update_derived_state(struct r600_context *rctx)
{
struct pipe_context * ctx = (struct pipe_context*)rctx;
- unsigned ps_dirty = 0;
+ unsigned ps_dirty = 0, blend_override;
if (!rctx->blitter->running) {
- /* Flush depth textures which need to be flushed. */
- if (rctx->vs_samplers.depth_texture_mask) {
- r600_flush_depth_textures(rctx, &rctx->vs_samplers);
- }
- if (rctx->ps_samplers.depth_texture_mask) {
- r600_flush_depth_textures(rctx, &rctx->ps_samplers);
- }
- }
+ unsigned i;
- if (rctx->chip_class < EVERGREEN) {
- r600_update_sampler_states(rctx);
+ /* Decompress textures if needed. */
+ for (i = 0; i < PIPE_SHADER_TYPES; i++) {
+ struct r600_samplerview_state *views = &rctx->samplers[i].views;
+ if (views->compressed_depthtex_mask) {
+ r600_decompress_depth_textures(rctx, views);
+ }
+ if (views->compressed_colortex_mask) {
+ r600_decompress_color_textures(rctx, views);
+ }
+ }
}
r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
- if (rctx->alpha_ref_dirty) {
- r600_update_alpha_ref(rctx);
- }
-
if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
(rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
(rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
if (ps_dirty)
r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
-
+
+ blend_override = (rctx->dual_src_blend &&
+ rctx->ps_shader->current->nr_ps_color_outputs < 2);
+
+ if (blend_override != rctx->blend_override) {
+ rctx->blend_override = blend_override;
+ r600_bind_blend_state_internal(rctx,
+ blend_override ? rctx->no_blend : rctx->blend);
+ }
+
if (rctx->chip_class >= EVERGREEN) {
evergreen_update_dual_export_state(rctx);
} else {
V_028A6C_OUTPRIM_TYPE_LINESTRIP,
V_028A6C_OUTPRIM_TYPE_LINESTRIP,
V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ V_028A6C_OUTPRIM_TYPE_TRISTRIP,
V_028A6C_OUTPRIM_TYPE_TRISTRIP
};
assert(mode < Elements(prim_conv));
return prim_conv[mode];
}
-void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
+static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct pipe_draw_info info = *dinfo;
struct pipe_index_buffer ib = {};
- unsigned prim, ls_mask = 0;
+ unsigned prim, ls_mask = 0, i;
struct r600_block *dirty_block = NULL, *next_block = NULL;
- struct r600_atom *state = NULL, *next_state = NULL;
struct radeon_winsys_cs *cs = rctx->cs;
uint64_t va;
uint8_t *ptr;
}
} else {
info.index_bias = info.start;
- if (info.count_from_stream_output) {
- r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
- }
}
if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
- r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
- r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control);
r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
if (prim == V_008958_DI_PT_LINELIST)
ls_mask = 1;
- else if (prim == V_008958_DI_PT_LINESTRIP)
+ else if (prim == V_008958_DI_PT_LINESTRIP ||
+ prim == V_008958_DI_PT_LINELOOP)
ls_mask = 2;
r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
r600_pipe_state_mod_reg(&rctx->vgt,
r600_context_pipe_state_set(rctx, &rctx->vgt);
+ /* Enable stream out if needed. */
+ if (rctx->streamout_start) {
+ r600_context_streamout_begin(rctx);
+ rctx->streamout_start = FALSE;
+ }
+
/* Emit states (the function expects that we emit at most 17 dwords here). */
r600_need_cs_space(rctx, 0, TRUE);
+ r600_flush_emit(rctx);
- LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
- r600_emit_atom(rctx, state);
+ for (i = 0; i < R600_NUM_ATOMS; i++) {
+ if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
+ continue;
+ }
+ r600_emit_atom(rctx, rctx->atoms[i]);
}
LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
}
- LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
- r600_context_block_resource_emit_dirty(rctx, dirty_block);
- }
rctx->pm4_dirty_cdwords = 0;
- /* Enable stream out if needed. */
- if (rctx->streamout_start) {
- r600_context_streamout_begin(rctx);
- rctx->streamout_start = FALSE;
- }
-
/* draw packet */
- cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
- cs->buf[cs->cdw++] = ib.index_size == 4 ?
- (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
- (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
cs->buf[cs->cdw++] = info.instance_count;
if (info.indexed) {
+ cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
+ cs->buf[cs->cdw++] = ib.index_size == 4 ?
+ (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
+ (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
+
va = r600_resource_va(ctx->screen, ib.buffer);
va += ib.offset;
cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
} else {
+ if (info.count_from_stream_output) {
+ struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
+ uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->filled_size);
+
+ r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
+
+ cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
+ cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
+ cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */
+ cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
+ cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
+ cs->buf[cs->cdw++] = 0; /* unused */
+
+ cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
+ cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->filled_size, RADEON_USAGE_READ);
+ }
+
cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
cs->buf[cs->cdw++] = info.count;
cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
(info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
}
- rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
-
/* Set the depth buffer as dirty. */
if (rctx->framebuffer.zsbuf) {
struct pipe_surface *surf = rctx->framebuffer.zsbuf;
- struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture;
+ struct r600_texture *rtex = (struct r600_texture *)surf->texture;
- rtex->dirty_db_mask |= 1 << surf->u.tex.level;
+ rtex->dirty_level_mask |= 1 << surf->u.tex.level;
+ }
+ if (rctx->compressed_cb_mask) {
+ struct pipe_surface *surf;
+ struct r600_texture *rtex;
+ unsigned mask = rctx->compressed_cb_mask;
+
+ do {
+ unsigned i = u_bit_scan(&mask);
+ surf = rctx->framebuffer.cbufs[i];
+ rtex = (struct r600_texture*)surf->texture;
+
+ rtex->dirty_level_mask |= 1 << surf->u.tex.level;
+
+ } while (mask);
}
pipe_resource_reference(&ib.buffer, NULL);
}
+void r600_draw_rectangle(struct blitter_context *blitter,
+ unsigned x1, unsigned y1, unsigned x2, unsigned y2, float depth,
+ enum blitter_attrib_type type, const union pipe_color_union *attrib)
+{
+ struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
+ struct pipe_viewport_state viewport;
+ struct pipe_resource *buf = NULL;
+ unsigned offset = 0;
+ float *vb;
+
+ if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
+ util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
+ return;
+ }
+
+ /* Some operations (like color resolve on r6xx) don't work
+ * with the conventional primitive types.
+ * One that works is PT_RECTLIST, which we use here. */
+
+ /* setup viewport */
+ viewport.scale[0] = 1.0f;
+ viewport.scale[1] = 1.0f;
+ viewport.scale[2] = 1.0f;
+ viewport.scale[3] = 1.0f;
+ viewport.translate[0] = 0.0f;
+ viewport.translate[1] = 0.0f;
+ viewport.translate[2] = 0.0f;
+ viewport.translate[3] = 0.0f;
+ rctx->context.set_viewport_state(&rctx->context, &viewport);
+
+ /* Upload vertices. The hw rectangle has only 3 vertices,
+ * I guess the 4th one is derived from the first 3.
+ * The vertex specification should match u_blitter's vertex element state. */
+ u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
+ vb[0] = x1;
+ vb[1] = y1;
+ vb[2] = depth;
+ vb[3] = 1;
+
+ vb[8] = x1;
+ vb[9] = y2;
+ vb[10] = depth;
+ vb[11] = 1;
+
+ vb[16] = x2;
+ vb[17] = y1;
+ vb[18] = depth;
+ vb[19] = 1;
+
+ if (attrib) {
+ memcpy(vb+4, attrib->f, sizeof(float)*4);
+ memcpy(vb+12, attrib->f, sizeof(float)*4);
+ memcpy(vb+20, attrib->f, sizeof(float)*4);
+ }
+
+ /* draw */
+ util_draw_vertex_buffer(&rctx->context, NULL, buf, offset,
+ R600_PRIM_RECTANGLE_LIST, 3, 2);
+ pipe_resource_reference(&buf, NULL);
+}
+
void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
struct r600_pipe_state *state,
uint32_t offset, uint32_t value,
range_id, block_id, NULL, 0);
}
-void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
- uint32_t offset, uint32_t value,
- struct r600_resource *bo,
- enum radeon_bo_usage usage)
-{
- if (bo) assert(usage);
-
- state->regs[state->nregs].id = offset;
- state->regs[state->nregs].block = NULL;
- state->regs[state->nregs].value = value;
- state->regs[state->nregs].bo = bo;
- state->regs[state->nregs].bo_usage = usage;
-
- state->nregs++;
- assert(state->nregs < R600_BLOCK_MAX_REG);
-}
-
uint32_t r600_translate_stencil_op(int s_op)
{
switch (s_op) {
return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
}
}
+
+/* keep this at the end of this file, please */
+void r600_init_common_state_functions(struct r600_context *rctx)
+{
+ rctx->context.create_fs_state = r600_create_ps_state;
+ rctx->context.create_vs_state = r600_create_vs_state;
+ rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
+ rctx->context.bind_blend_state = r600_bind_blend_state;
+ rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
+ rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
+ rctx->context.bind_fs_state = r600_bind_ps_state;
+ rctx->context.bind_rasterizer_state = r600_bind_rs_state;
+ rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
+ rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
+ rctx->context.bind_vs_state = r600_bind_vs_state;
+ rctx->context.delete_blend_state = r600_delete_state;
+ rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
+ rctx->context.delete_fs_state = r600_delete_ps_state;
+ rctx->context.delete_rasterizer_state = r600_delete_rs_state;
+ rctx->context.delete_sampler_state = r600_delete_sampler_state;
+ rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
+ rctx->context.delete_vs_state = r600_delete_vs_state;
+ rctx->context.set_blend_color = r600_set_blend_color;
+ rctx->context.set_clip_state = r600_set_clip_state;
+ rctx->context.set_constant_buffer = r600_set_constant_buffer;
+ rctx->context.set_sample_mask = r600_set_sample_mask;
+ rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
+ rctx->context.set_viewport_state = r600_set_viewport_state;
+ rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
+ rctx->context.set_index_buffer = r600_set_index_buffer;
+ rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
+ rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
+ rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
+ rctx->context.texture_barrier = r600_texture_barrier;
+ rctx->context.create_stream_output_target = r600_create_so_target;
+ rctx->context.stream_output_target_destroy = r600_so_target_destroy;
+ rctx->context.set_stream_output_targets = r600_set_so_targets;
+ rctx->context.draw_vbo = r600_draw_vbo;
+}
projects / mesa.git / blobdiff