void (*emit)(struct r600_context *ctx, struct r600_atom *state),
unsigned num_dw)
{
- assert(id < R600_MAX_ATOM);
+ assert(id < R600_NUM_ATOMS);
assert(rctx->atoms[id] == NULL);
rctx->atoms[id] = atom;
atom->id = id;
}
}
-static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
+static unsigned r600_conv_pipe_prim(unsigned prim)
{
- static const int prim_conv[] = {
+ static const unsigned prim_conv[] = {
V_008958_DI_PT_POINTLIST,
V_008958_DI_PT_LINELIST,
V_008958_DI_PT_LINELOOP,
V_008958_DI_PT_QUADLIST,
V_008958_DI_PT_QUADSTRIP,
V_008958_DI_PT_POLYGON,
- -1,
- -1,
- -1,
- -1,
+ V_008958_DI_PT_LINELIST_ADJ,
+ V_008958_DI_PT_LINESTRIP_ADJ,
+ V_008958_DI_PT_TRILIST_ADJ,
+ V_008958_DI_PT_TRISTRIP_ADJ,
V_008958_DI_PT_RECTLIST
};
-
- *prim = prim_conv[pprim];
- if (*prim == -1) {
- fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
- return false;
- }
- return true;
+ return prim_conv[prim];
}
/* common state between evergreen and r600 */
const struct pipe_blend_color *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- if (rstate == NULL)
- return;
+ rctx->blend_color.state = *state;
+ r600_atom_dirty(rctx, &rctx->blend_color.atom);
+}
+
+void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct pipe_blend_color *state = &rctx->blend_color.state;
- rstate->id = R600_PIPE_STATE_BLEND_COLOR;
- r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
- r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
- r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
- r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
+ r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
+ r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
+ r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
+ r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
+ r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
+}
- free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
- rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
- r600_context_pipe_state_set(rctx, rstate);
+void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
+
+ r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
+ r600_write_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, a->vgt_multi_prim_ib_reset_indx);
+}
+
+void r600_emit_vgt2_state(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct r600_vgt2_state *a = (struct r600_vgt2_state *)atom;
+
+ r600_write_context_reg(cs, R_028408_VGT_INDX_OFFSET, a->vgt_indx_offset);
+}
+
+static void r600_set_clip_state(struct pipe_context *ctx,
+ const struct pipe_clip_state *state)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct pipe_constant_buffer cb;
+
+ rctx->clip_state.state = *state;
+ r600_atom_dirty(rctx, &rctx->clip_state.atom);
+
+ cb.buffer = NULL;
+ cb.user_buffer = state->ucp;
+ cb.buffer_offset = 0;
+ cb.buffer_size = 4*4*8;
+ ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
+ pipe_resource_reference(&cb.buffer, NULL);
}
static void r600_set_stencil_ref(struct pipe_context *ctx,
const struct r600_stencil_ref *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- if (rstate == NULL)
- return;
+ rctx->stencil_ref.state = *state;
+ r600_atom_dirty(rctx, &rctx->stencil_ref.atom);
+}
- rstate->id = R600_PIPE_STATE_STENCIL_REF;
- r600_pipe_state_add_reg(rstate,
- R_028430_DB_STENCILREFMASK,
- S_028430_STENCILREF(state->ref_value[0]) |
- S_028430_STENCILMASK(state->valuemask[0]) |
- S_028430_STENCILWRITEMASK(state->writemask[0]));
- r600_pipe_state_add_reg(rstate,
- R_028434_DB_STENCILREFMASK_BF,
- S_028434_STENCILREF_BF(state->ref_value[1]) |
- S_028434_STENCILMASK_BF(state->valuemask[1]) |
- S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
-
- free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
- rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
- r600_context_pipe_state_set(rctx, rstate);
+void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
+
+ r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
+ r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
+ S_028430_STENCILREF(a->state.ref_value[0]) |
+ S_028430_STENCILMASK(a->state.valuemask[0]) |
+ S_028430_STENCILWRITEMASK(a->state.writemask[0]));
+ r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
+ S_028434_STENCILREF_BF(a->state.ref_value[1]) |
+ S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
+ S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
}
static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
struct r600_stencil_ref ref;
- rctx->stencil_ref = *state;
+ rctx->stencil_ref.pipe_state = *state;
if (!dsa)
return;
rctx->states[rstate->id] = rstate;
r600_context_pipe_state_set(rctx, rstate);
- ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
- ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
+ ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
+ ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
ref.valuemask[0] = dsa->valuemask[0];
ref.valuemask[1] = dsa->valuemask[1];
ref.writemask[0] = dsa->writemask[0];
rctx->sprite_coord_enable = rs->sprite_coord_enable;
rctx->two_side = rs->two_side;
rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
- rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
rctx->multisample_enable = rs->multisample_enable;
rctx->rasterizer = rs;
r600_polygon_offset_update(rctx);
}
+ /* Update clip_misc_state. */
+ if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
+ rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
+ rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
+ rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
+ r600_atom_dirty(rctx, &rctx->clip_misc_state.atom);
+ }
+
/* Workaround for a missing scissor enable on r600. */
if (rctx->chip_class == R600) {
if (rs->scissor_enable != rctx->scissor_enable) {
}
static void r600_set_viewport_state(struct pipe_context *ctx,
- const struct pipe_viewport_state *state)
+ const struct pipe_viewport_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- if (rstate == NULL)
- return;
+ rctx->viewport.state = *state;
+ r600_atom_dirty(rctx, &rctx->viewport.atom);
+}
- rctx->viewport = *state;
- rstate->id = R600_PIPE_STATE_VIEWPORT;
- r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
- r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
- r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
- r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
- r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
- r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
-
- free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
- rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
- r600_context_pipe_state_set(rctx, rstate);
+void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct pipe_viewport_state *state = &rctx->viewport.state;
+
+ r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
+ r600_write_value(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
+ r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
+ r600_write_value(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
+ r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
+ r600_write_value(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
+ r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
}
static void *r600_create_vertex_elements(struct pipe_context *ctx, unsigned count,
}
/* Compute the key for the hw shader variant */
-static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx,
+static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
struct r600_pipe_shader_selector * sel)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- unsigned key;
+ struct r600_shader_key key;
+ memset(&key, 0, sizeof(key));
if (sel->type == PIPE_SHADER_FRAGMENT) {
- key = rctx->two_side |
- ((rctx->alpha_to_one && rctx->multisample_enable && !rctx->cb0_is_integer) << 1) |
- (MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 2);
- } else
- key = 0;
-
+ key.color_two_side = rctx->two_side;
+ key.alpha_to_one = rctx->alpha_to_one &&
+ rctx->multisample_enable &&
+ !rctx->framebuffer.cb0_is_integer;
+ key.dual_src_blend = rctx->dual_src_blend;
+ key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
+ }
return key;
}
struct r600_pipe_shader_selector* sel,
unsigned *dirty)
{
- unsigned key;
+ struct r600_shader_key key;
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_shader * shader = NULL;
int r;
* This path is also used for most shaders that don't need multiple
* variants, it will cost just a computation of the key and this
* test. */
- if (likely(sel->current && sel->current->key == key)) {
+ if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
return 0;
}
if (sel->num_shaders > 1) {
struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
- while (c && c->key != key) {
+ while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
p = c;
c = c->next_variant;
}
shader = CALLOC(1, sizeof(struct r600_pipe_shader));
shader->selector = sel;
- r = r600_pipe_shader_create(ctx, shader);
+ r = r600_pipe_shader_create(ctx, shader, key);
if (unlikely(r)) {
- R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
- sel->type, key, r);
+ R600_ERR("Failed to build shader variant (type=%u) %d\n",
+ sel->type, r);
sel->current = NULL;
return r;
}
if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
r600_adjust_gprs(rctx);
+
+ /* Update clip misc state. */
+ if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
+ rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
+ rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
+ rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
+ r600_atom_dirty(rctx, &rctx->clip_misc_state.atom);
+ }
}
}
return prim_conv[mode];
}
+void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx->cs;
+ struct r600_clip_misc_state *state = &rctx->clip_misc_state;
+
+ r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
+ state->pa_cl_clip_cntl |
+ (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
+ r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
+ state->pa_cl_vs_out_cntl |
+ (state->clip_plane_enable & state->clip_dist_write));
+}
+
static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct pipe_draw_info info = *dinfo;
struct pipe_index_buffer ib = {};
- unsigned prim, ls_mask = 0, i;
+ unsigned i;
struct r600_block *dirty_block = NULL, *next_block = NULL;
struct radeon_winsys_cs *cs = rctx->cs;
uint64_t va;
uint8_t *ptr;
- if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
- !r600_conv_pipe_prim(info.mode, &prim)) {
+ if (!info.count && (info.indexed || !info.count_from_stream_output)) {
assert(0);
return;
}
info.index_bias = info.start;
}
- if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
- rctx->vgt.id = R600_PIPE_STATE_VGT;
- rctx->vgt.nregs = 0;
- r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
- r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
- r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
- r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
- r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
- r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
- r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
- }
-
- rctx->vgt.nregs = 0;
- r600_pipe_state_mod_reg(&rctx->vgt, prim);
- r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
- r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
- r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
- r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
- r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
-
- if (prim == V_008958_DI_PT_LINELIST)
- ls_mask = 1;
- else if (prim == V_008958_DI_PT_LINESTRIP ||
- prim == V_008958_DI_PT_LINELOOP)
- ls_mask = 2;
- r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
- r600_pipe_state_mod_reg(&rctx->vgt,
- rctx->vs_shader->current->pa_cl_vs_out_cntl |
- (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
- r600_pipe_state_mod_reg(&rctx->vgt,
- rctx->pa_cl_clip_cntl |
- (rctx->vs_shader->current->shader.clip_dist_write ||
- rctx->vs_shader->current->shader.vs_prohibit_ucps ?
- 0 : rctx->rasterizer->clip_plane_enable & 0x3F));
-
- r600_context_pipe_state_set(rctx, &rctx->vgt);
-
/* Enable stream out if needed. */
if (rctx->streamout_start) {
r600_context_streamout_begin(rctx);
rctx->streamout_start = FALSE;
}
+ /* Set the index offset and multi primitive */
+ if (rctx->vgt2_state.vgt_indx_offset != info.index_bias) {
+ rctx->vgt2_state.vgt_indx_offset = info.index_bias;
+ r600_atom_dirty(rctx, &rctx->vgt2_state.atom);
+ }
+ if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
+ rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index) {
+ rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
+ rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
+ r600_atom_dirty(rctx, &rctx->vgt_state.atom);
+ }
+
/* Emit states (the function expects that we emit at most 17 dwords here). */
r600_need_cs_space(rctx, 0, TRUE);
r600_flush_emit(rctx);
- for (i = 0; i < R600_MAX_ATOM; i++) {
+ for (i = 0; i < R600_NUM_ATOMS; i++) {
if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
continue;
}
}
rctx->pm4_dirty_cdwords = 0;
- /* draw packet */
+ /* Update start instance. */
+ if (rctx->last_start_instance != info.start_instance) {
+ r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
+ rctx->last_start_instance = info.start_instance;
+ }
+
+ /* Update the primitive type. */
+ if (rctx->last_primitive_type != info.mode) {
+ unsigned ls_mask = 0;
+
+ if (info.mode == PIPE_PRIM_LINES)
+ ls_mask = 1;
+ else if (info.mode == PIPE_PRIM_LINE_STRIP ||
+ info.mode == PIPE_PRIM_LINE_LOOP)
+ ls_mask = 2;
+
+ r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
+ S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
+ r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
+ r600_conv_prim_to_gs_out(info.mode));
+ r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
+ r600_conv_pipe_prim(info.mode));
+
+ rctx->last_primitive_type = info.mode;
+ }
+
+ /* Draw packets. */
cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
cs->buf[cs->cdw++] = info.instance_count;
if (info.indexed) {
}
/* Set the depth buffer as dirty. */
- if (rctx->framebuffer.zsbuf) {
- struct pipe_surface *surf = rctx->framebuffer.zsbuf;
+ if (rctx->framebuffer.state.zsbuf) {
+ struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
struct r600_texture *rtex = (struct r600_texture *)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
}
- if (rctx->compressed_cb_mask) {
+ if (rctx->framebuffer.compressed_cb_mask) {
struct pipe_surface *surf;
struct r600_texture *rtex;
- unsigned mask = rctx->compressed_cb_mask;
+ unsigned mask = rctx->framebuffer.compressed_cb_mask;
do {
unsigned i = u_bit_scan(&mask);
- surf = rctx->framebuffer.cbufs[i];
+ surf = rctx->framebuffer.state.cbufs[i];
rtex = (struct r600_texture*)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
rctx->context.delete_vs_state = r600_delete_vs_state;
rctx->context.set_blend_color = r600_set_blend_color;
+ rctx->context.set_clip_state = r600_set_clip_state;
rctx->context.set_constant_buffer = r600_set_constant_buffer;
rctx->context.set_sample_mask = r600_set_sample_mask;
rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
projects / mesa.git / blobdiff