r600g: enable thread offloading
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
index 7ffea6961de9b01516aa3c3abae1c8956f48da13..7b5a3e74a26f818028ef4492316a550e4df90bb7 100644 (file)
 #include <util/u_math.h>
 #include <util/u_inlines.h>
 #include <util/u_memory.h>
-#include "state_tracker/drm_driver.h"
 #include "pipebuffer/pb_buffer.h"
 #include "r600_pipe.h"
 #include "r600_resource.h"
-#include "r600_state_inlines.h"
 #include "r600d.h"
 #include "r600_formats.h"
 
@@ -68,7 +66,7 @@ static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600
                                  rtransfer->staging_texture,
                                  0, &sbox);
 
-        ctx->flush(ctx, NULL);
+       r600_flush(ctx, NULL, RADEON_FLUSH_ASYNC);
 }
 
 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
@@ -240,13 +238,14 @@ static void r600_setup_miptree(struct pipe_screen *screen,
                               unsigned array_mode)
 {
        struct pipe_resource *ptex = &rtex->resource.b.b.b;
-       struct radeon *radeon = (struct radeon *)screen->winsys;
+       struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
        enum chip_class chipc = r600_get_family_class(radeon);
        unsigned size, layer_size, i, offset;
-       unsigned nblocksx, nblocksy;
+       unsigned nblocksx, nblocksy, extra_size = 0;
 
        for (i = 0, offset = 0; i <= ptex->last_level; i++) {
                unsigned blocksize = util_format_get_blocksize(ptex->format);
+               unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 
                r600_texture_set_array_mode(screen, rtex, i, array_mode);
 
@@ -265,9 +264,13 @@ static void r600_setup_miptree(struct pipe_screen *screen,
                else
                        size = layer_size * ptex->array_size;
 
+               /* evergreen stores depth and stencil separately */
+               if ((chipc >= EVERGREEN) && util_format_is_depth_or_stencil(ptex->format))
+                       extra_size = align(extra_size + (nblocksx * nblocksy * 1), base_align);
+
                /* align base image and start of miptree */
                if ((i == 0) || (i == 1))
-                       offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
+                       offset = align(offset, base_align);
                rtex->offset[i] = offset;
                rtex->layer_size[i] = layer_size;
                rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
@@ -275,7 +278,7 @@ static void r600_setup_miptree(struct pipe_screen *screen,
 
                offset += size;
        }
-       rtex->size = offset;
+       rtex->size = offset + extra_size;
 }
 
 /* Figure out whether u_blitter will fallback to a transfer operation.
@@ -309,7 +312,14 @@ static boolean permit_hardware_blit(struct pipe_screen *screen,
                                 PIPE_BIND_SAMPLER_VIEW))
                return FALSE;
 
-       return TRUE;
+       switch (res->usage) {
+       case PIPE_USAGE_STREAM:
+       case PIPE_USAGE_STAGING:
+               return FALSE;
+
+       default:
+               return TRUE;
+       }
 }
 
 static boolean r600_texture_get_handle(struct pipe_screen* screen,
@@ -318,7 +328,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
 {
        struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
        struct r600_resource *resource = &rtex->resource;
-       struct radeon *radeon = (struct radeon *)screen->winsys;
+       struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
 
        return r600_bo_get_winsys_handle(radeon, resource->bo,
                        rtex->pitch_in_bytes[0], whandle);
@@ -329,13 +339,12 @@ static void r600_texture_destroy(struct pipe_screen *screen,
 {
        struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
        struct r600_resource *resource = &rtex->resource;
-       struct radeon *radeon = (struct radeon *)screen->winsys;
 
        if (rtex->flushed_depth_texture)
                pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 
        if (resource->bo) {
-               r600_bo_reference(radeon, &resource->bo, NULL);
+               r600_bo_reference(&resource->bo, NULL);
        }
        FREE(rtex);
 }
@@ -362,7 +371,7 @@ r600_texture_create_object(struct pipe_screen *screen,
 {
        struct r600_resource_texture *rtex;
        struct r600_resource *resource;
-       struct radeon *radeon = (struct radeon *)screen->winsys;
+       struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
 
        rtex = CALLOC_STRUCT(r600_resource_texture);
        if (rtex == NULL)
@@ -472,8 +481,9 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
                                               const struct pipe_resource *templ,
                                               struct winsys_handle *whandle)
 {
-       struct radeon *rw = (struct radeon*)screen->winsys;
+       struct radeon *rw = ((struct r600_screen*)screen)->radeon;
        struct r600_bo *bo = NULL;
+       unsigned stride = 0;
        unsigned array_mode = 0;
 
        /* Support only 2D textures without mipmaps */
@@ -481,15 +491,13 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
              templ->depth0 != 1 || templ->last_level != 0)
                return NULL;
 
-       bo = r600_bo_handle(rw, whandle->handle, &array_mode);
+       bo = r600_bo_handle(rw, whandle, &stride, &array_mode);
        if (bo == NULL) {
                return NULL;
        }
 
        return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
-                                                                 whandle->stride,
-                                                                 0,
-                                                                 bo);
+                                                                 stride, 0, bo);
 }
 
 int r600_texture_depth_flush(struct pipe_context *ctx,
@@ -637,7 +645,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
                if (usage & PIPE_TRANSFER_READ) {
                        r600_copy_to_staging_texture(ctx, trans);
                        /* Always referenced in the blit. */
-                        ctx->flush(ctx, NULL);
+                       r600_flush(ctx, NULL, 0);
                }
                return &trans->transfer;
        }
@@ -673,12 +681,12 @@ void r600_texture_transfer_destroy(struct pipe_context *ctx,
 void* r600_texture_transfer_map(struct pipe_context *ctx,
                                struct pipe_transfer* transfer)
 {
+       struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
        struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
        struct r600_bo *bo;
        enum pipe_format format = transfer->resource->format;
-       struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
+       struct radeon *radeon = rctx->screen->radeon;
        unsigned offset = 0;
-       unsigned usage = 0;
        char *map;
 
        if (rtransfer->staging_texture) {
@@ -696,30 +704,7 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
                        transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
        }
 
-       if (transfer->usage & PIPE_TRANSFER_WRITE) {
-               usage |= PB_USAGE_CPU_WRITE;
-
-               if (transfer->usage & PIPE_TRANSFER_DISCARD) {
-               }
-
-               if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
-               }
-       }
-
-       if (transfer->usage & PIPE_TRANSFER_READ) {
-               usage |= PB_USAGE_CPU_READ;
-       }
-
-       if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
-               usage |= PB_USAGE_DONTBLOCK;
-       }
-
-       if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
-               usage |= PB_USAGE_UNSYNCHRONIZED;
-       }
-
-       map = r600_bo_map(radeon, bo, usage, ctx);
-       if (!map) {
+       if (!(map = r600_bo_map(radeon, bo, rctx->ctx.cs, transfer->usage))) {
                return NULL;
        }
 
@@ -730,7 +715,7 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
                                 struct pipe_transfer* transfer)
 {
        struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
-       struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
+       struct radeon *radeon = ((struct r600_screen*)ctx->screen)->radeon;
        struct r600_bo *bo;
 
        if (rtransfer->staging_texture) {
@@ -767,11 +752,7 @@ static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
        };
 
        if (swizzle_view) {
-               /* Combine two sets of swizzles. */
-               for (i = 0; i < 4; i++) {
-                       swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
-                               swizzle_format[swizzle_view[i]] : swizzle_view[i];
-               }
+               util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
        } else {
                memcpy(swizzle, swizzle_format, 4);
        }
@@ -847,6 +828,12 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen,
                        result = FMT_8;
                        word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
                        goto out_word4;
+               case PIPE_FORMAT_Z32_FLOAT:
+                       result = FMT_32_FLOAT;
+                       goto out_word4;
+               case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+                       result = FMT_X24_8_32_FLOAT;
+                       goto out_word4;
                default:
                        goto out_unknown;
                }
@@ -1082,8 +1069,9 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen,
                                goto out_word4;
                        }
                }
-
+               goto out_unknown;
        }
+
 out_word4:
        if (word4_p)
                *word4_p = word4;