struct radeon_surface *surface,
const struct pipe_resource *ptex,
unsigned array_mode,
- bool is_flushed_depth)
+ bool is_flushed_depth,
+ bool from_ddx)
{
const struct util_format_description *desc =
util_format_description(ptex->format);
surface->array_size = 1;
surface->last_level = ptex->last_level;
+ if (from_ddx) {
+ surface->npix_y = align(surface->npix_y, 8);
+ }
+
if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
surface->bpe = 4; /* stencil is allocated separately on evergreen */
unsigned base_align = rtex->surface.bo_alignment;
unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage;
- if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, usage)) {
+ if (!r600_init_resource(rscreen, resource, rtex->size, base_align, FALSE, usage)) {
FREE(rtex);
return NULL;
}
}
r = r600_init_surface(rscreen, &surface, templ, array_mode,
- templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
+ templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH,
+ false);
if (r) {
return NULL;
}
surface->base.format = templ->format;
surface->base.width = width;
surface->base.height = height;
- surface->base.usage = templ->usage;
surface->base.u = templ->u;
return &surface->base;
}
else
array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
- r = r600_init_surface(rscreen, &surface, templ, array_mode, false);
+ r = r600_init_surface(rscreen, &surface, templ, array_mode, false, true);
if (r) {
return NULL;
}