}
}
-static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_resource_texture *rtex)
+static void r600_setup_miptree(struct r600_resource_texture *rtex)
{
struct pipe_resource *ptex = &rtex->resource.base.b;
unsigned long w, h, pitch, size, layer_size, i, offset;
{
struct r600_resource_texture *rtex;
struct r600_resource *resource;
- struct r600_screen *rscreen = r600_screen(screen);
+ struct radeon *radeon = (struct radeon *)screen->winsys;
rtex = CALLOC_STRUCT(r600_resource_texture);
if (!rtex) {
resource->base.vtbl = &r600_texture_vtbl;
pipe_reference_init(&resource->base.b.reference, 1);
resource->base.b.screen = screen;
- r600_setup_miptree(rscreen, rtex);
+ r600_setup_miptree(rtex);
/* FIXME alignment 4096 enought ? too much ? */
resource->domain = r600_domain_from_usage(resource->base.b.bind);
- resource->bo = radeon_bo(rscreen->rw, 0, rtex->size, 4096, NULL);
+ resource->size = rtex->size;
+ resource->bo = radeon_ws_bo(radeon, rtex->size, 4096, 0);
if (resource->bo == NULL) {
FREE(rtex);
return NULL;
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
struct r600_resource *resource = &rtex->resource;
- struct r600_screen *rscreen = r600_screen(screen);
+ struct radeon *radeon = (struct radeon *)screen->winsys;
if (resource->bo) {
- radeon_bo_decref(rscreen->rw, resource->bo);
+ radeon_ws_bo_reference(radeon, &resource->bo, NULL);
}
if (rtex->uncompressed) {
- radeon_bo_decref(rscreen->rw, rtex->uncompressed);
+ radeon_ws_bo_reference(radeon, &rtex->uncompressed, NULL);
}
r600_texture_destroy_state(ptex);
FREE(rtex);
struct radeon *rw = (struct radeon*)screen->winsys;
struct r600_resource_texture *rtex;
struct r600_resource *resource;
- struct radeon_bo *bo = NULL;
-
- bo = radeon_bo(rw, whandle->handle, 0, 0, NULL);
- if (bo == NULL) {
- return NULL;
- }
+ struct radeon_ws_bo *bo = NULL;
/* Support only 2D textures without mipmaps */
if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
if (rtex == NULL)
return NULL;
+ bo = radeon_ws_bo_handle(rw, whandle->handle);
+ if (bo == NULL) {
+ FREE(rtex);
+ return NULL;
+ }
+
resource = &rtex->resource;
resource->base.b = *templ;
resource->base.vtbl = &r600_texture_vtbl;
void* r600_texture_transfer_map(struct pipe_context *ctx,
struct pipe_transfer* transfer)
{
+ struct r600_screen *rscreen = r600_screen(ctx->screen);
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct radeon_bo *bo;
+ struct radeon_ws_bo *bo;
enum pipe_format format = transfer->resource->format;
- struct r600_screen *rscreen = r600_screen(ctx->screen);
+ struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
struct r600_resource_texture *rtex;
unsigned long offset = 0;
char *map;
bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
} else {
rtex = (struct r600_resource_texture*)transfer->resource;
- if (rtex->depth) {
+ if (rtex->depth && rscreen->chip_class != EVERGREEN) {
r = r600_texture_from_depth(ctx, rtex, transfer->sr.level);
if (r) {
return NULL;
transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
}
- if (radeon_bo_map(rscreen->rw, bo)) {
+ map = radeon_ws_bo_map(radeon, bo, 0, r600_context(ctx));
+ if (!map) {
return NULL;
}
- radeon_bo_wait(rscreen->rw, bo);
+ radeon_ws_bo_wait(radeon, bo);
- map = bo->data;
return map + offset;
}
struct pipe_transfer* transfer)
{
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct r600_screen *rscreen = r600_screen(ctx->screen);
+ struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
struct r600_resource_texture *rtex;
- struct radeon_bo *bo;
+ struct radeon_ws_bo *bo;
if (rtransfer->linear_texture) {
bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
bo = ((struct r600_resource *)transfer->resource)->bo;
}
}
- radeon_bo_unmap(rscreen->rw, bo);
+ radeon_ws_bo_unmap(radeon, bo);
}
struct u_resource_vtbl r600_texture_vtbl =
default:
break;
}
-
+
/* S3TC formats. TODO */
if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
goto out_unknown;
if (desc->channel[0].size == 5 &&
desc->channel[1].size == 6 &&
desc->channel[2].size == 5) {
- result |= V_0280A0_COLOR_5_6_5;
+ result = V_0280A0_COLOR_5_6_5;
goto out_word4;
}
goto out_unknown;
desc->channel[1].size == 5 &&
desc->channel[2].size == 5 &&
desc->channel[3].size == 1) {
- result |= V_0280A0_COLOR_1_5_5_5;
+ result = V_0280A0_COLOR_1_5_5_5;
goto out_word4;
}
if (desc->channel[0].size == 10 &&
desc->channel[1].size == 10 &&
desc->channel[2].size == 10 &&
desc->channel[3].size == 2) {
- result |= V_0280A0_COLOR_10_10_10_2;
+ result = V_0280A0_COLOR_10_10_10_2;
goto out_word4;
}
goto out_unknown;
case 4:
switch (desc->nr_channels) {
case 2:
- result |= V_0280A0_COLOR_4_4;
+ result = V_0280A0_COLOR_4_4;
goto out_word4;
case 4:
- result |= V_0280A0_COLOR_4_4_4_4;
+ result = V_0280A0_COLOR_4_4_4_4;
goto out_word4;
}
goto out_unknown;
case 8:
switch (desc->nr_channels) {
case 1:
- result |= V_0280A0_COLOR_8;
+ result = V_0280A0_COLOR_8;
goto out_word4;
case 2:
- result |= V_0280A0_COLOR_8_8;
+ result = V_0280A0_COLOR_8_8;
goto out_word4;
case 4:
- result |= V_0280A0_COLOR_8_8_8_8;
+ result = V_0280A0_COLOR_8_8_8_8;
goto out_word4;
}
goto out_unknown;
case 16:
switch (desc->nr_channels) {
case 1:
- result |= V_0280A0_COLOR_16;
+ result = V_0280A0_COLOR_16;
goto out_word4;
case 2:
- result |= V_0280A0_COLOR_16_16;
+ result = V_0280A0_COLOR_16_16;
goto out_word4;
case 4:
- result |= V_0280A0_COLOR_16_16_16_16;
+ result = V_0280A0_COLOR_16_16_16_16;
goto out_word4;
}
}
case 16:
switch (desc->nr_channels) {
case 1:
- result |= V_0280A0_COLOR_16_FLOAT;
+ result = V_0280A0_COLOR_16_FLOAT;
goto out_word4;
case 2:
- result |= V_0280A0_COLOR_16_16_FLOAT;
+ result = V_0280A0_COLOR_16_16_FLOAT;
goto out_word4;
case 4:
- result |= V_0280A0_COLOR_16_16_16_16_FLOAT;
+ result = V_0280A0_COLOR_16_16_16_16_FLOAT;
goto out_word4;
}
goto out_unknown;
case 32:
switch (desc->nr_channels) {
case 1:
- result |= V_0280A0_COLOR_32_FLOAT;
+ result = V_0280A0_COLOR_32_FLOAT;
goto out_word4;
case 2:
- result |= V_0280A0_COLOR_32_32_FLOAT;
+ result = V_0280A0_COLOR_32_32_FLOAT;
goto out_word4;
case 4:
- result |= V_0280A0_COLOR_32_32_32_32_FLOAT;
+ result = V_0280A0_COLOR_32_32_32_32_FLOAT;
goto out_word4;
}
}
/* allocate uncompressed texture */
if (rtexture->uncompressed == NULL) {
- rtexture->uncompressed = radeon_bo(rscreen->rw, 0, rtexture->size, 4096, NULL);
+ rtexture->uncompressed = radeon_ws_bo(rscreen->rw, rtexture->size, 4096, 0);
if (rtexture->uncompressed == NULL) {
return -ENOMEM;
}
return 0;
}
-static void r600_texture_state_scissor(struct r600_screen *rscreen,
- struct r600_resource_texture *rtexture,
- unsigned level)
-{
- struct radeon_state *rstate = &rtexture->scissor[level];
-
- radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
- /* set states (most default value are 0 and struct already
- * initialized to 0, thus avoid resetting them)
- */
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
- rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
- rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
- rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
- rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
- rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
- rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
- rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
- rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
- rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
- rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
-
- radeon_state_pm4(rstate);
-}
-
-static void r600_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
-{
- struct radeon_state *rstate;
- struct r600_resource *rbuffer;
- unsigned pitch, slice;
- unsigned color_info;
- unsigned format, swap, ntype;
- const struct util_format_description *desc;
-
- rstate = &rtexture->cb[cb][level];
- radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
- rbuffer = &rtexture->resource;
-
- /* set states (most default value are 0 and struct already
- * initialized to 0, thus avoid resetting them)
- */
- pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
- slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
- ntype = 0;
- desc = util_format_description(rbuffer->base.b.format);
- if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
- ntype = V_0280A0_NUMBER_SRGB;
- format = r600_translate_colorformat(rtexture->resource.base.b.format);
- swap = r600_translate_colorswap(rtexture->resource.base.b.format);
- if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
- rstate->bo[2] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
- rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
- rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
- rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
- rstate->nbo = 3;
- color_info = 0;
- } else {
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
- rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
- rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
- rstate->nbo = 3;
- color_info = S_0280A0_SOURCE_FORMAT(1);
- }
- color_info |= S_0280A0_FORMAT(format) |
- S_0280A0_COMP_SWAP(swap) |
- S_0280A0_BLEND_CLAMP(1) |
- S_0280A0_NUMBER_TYPE(ntype);
- rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
- rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
- rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
- S_028060_SLICE_TILE_MAX(slice);
-
- radeon_state_pm4(rstate);
-}
-static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
-{
- struct radeon_state *rstate = &rtexture->db[level];
- struct r600_resource *rbuffer;
- unsigned pitch, slice, format;
-
- radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
- rbuffer = &rtexture->resource;
- rtexture->tilled = 1;
- rtexture->array_mode = 2;
- rtexture->tile_type = 1;
- rtexture->depth = 1;
-
- /* set states (most default value are 0 and struct already
- * initialized to 0, thus avoid resetting them)
- */
- pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
- slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
- format = r600_translate_dbformat(rbuffer->base.b.format);
- rstate->states[R600_DB__DB_DEPTH_BASE] = rtexture->offset[level] >> 8;
- rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtexture->array_mode) |
- S_028010_FORMAT(format);
- rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
- rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
- rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
- S_028000_SLICE_TILE_MAX(slice);
- rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
- rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
- rstate->nbo = 1;
-
- radeon_state_pm4(rstate);
-}
int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
{
struct r600_screen *rscreen = r600_screen(ctx->screen);
+ struct r600_context *rctx = r600_context(ctx);
if (!rtexture->scissor[level].cpm4) {
- r600_texture_state_scissor(rscreen, rtexture, level);
+ rctx->vtbl->texture_state_scissor(rscreen, rtexture, level);
}
return 0;
}
-static void r600_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
-{
- struct radeon_state *rstate = &rtexture->viewport[level];
-
- radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
-
- /* set states (most default value are 0 and struct already
- * initialized to 0, thus avoid resetting them)
- */
- rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0);
- rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0);
- rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0);
- rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0);
- rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
- rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
- rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
- rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
-
- radeon_state_pm4(rstate);
-}
-
int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
{
struct r600_screen *rscreen = r600_screen(ctx->screen);
+ struct r600_context *rctx = r600_context(ctx);
if (!rtexture->cb[cb][level].cpm4) {
- r600_texture_state_cb(rscreen, rtexture, cb, level);
+ rctx->vtbl->texture_state_cb(rscreen, rtexture, cb, level);
}
return 0;
}
int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
{
struct r600_screen *rscreen = r600_screen(ctx->screen);
+ struct r600_context *rctx = r600_context(ctx);
if (!rtexture->db[level].cpm4) {
- r600_texture_state_db(rscreen, rtexture, level);
+ rctx->vtbl->texture_state_db(rscreen, rtexture, level);
}
return 0;
}
int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
{
struct r600_screen *rscreen = r600_screen(ctx->screen);
+ struct r600_context *rctx = r600_context(ctx);
if (!rtexture->viewport[level].cpm4) {
- r600_texture_state_viewport(rscreen, rtexture, level);
+ rctx->vtbl->texture_state_viewport(rscreen, rtexture, level);
}
return 0;
}
projects / mesa.git / blobdiff