#include <util/u_math.h>
#include <util/u_inlines.h>
#include <util/u_memory.h>
-#include "state_tracker/drm_driver.h"
#include "pipebuffer/pb_buffer.h"
#include "r600_pipe.h"
#include "r600_resource.h"
-#include "r600_state_inlines.h"
#include "r600d.h"
#include "r600_formats.h"
rtransfer->staging_texture,
0, &sbox);
- ctx->flush(ctx, 0, NULL);
+ r600_flush(ctx, NULL, RADEON_FLUSH_ASYNC);
}
unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
switch (rtex->resource.b.b.b.target) {
case PIPE_TEXTURE_3D:
case PIPE_TEXTURE_CUBE:
- return offset + layer * rtex->layer_size[level];
default:
- assert(layer == 0);
- return offset;
+ return offset + layer * rtex->layer_size[level];
}
}
{
struct pipe_resource *ptex = &rtex->resource.b.b.b;
unsigned nblocksx, block_align, width;
- unsigned blocksize = util_format_get_blocksize(ptex->format);
+ unsigned blocksize = util_format_get_blocksize(rtex->real_format);
if (rtex->pitch_override)
return rtex->pitch_override / blocksize;
width = mip_minify(ptex->width0, level);
- nblocksx = util_format_get_nblocksx(ptex->format, width);
+ nblocksx = util_format_get_nblocksx(rtex->real_format, width);
- block_align = r600_get_block_alignment(screen, ptex->format,
+ block_align = r600_get_block_alignment(screen, rtex->real_format,
rtex->array_mode[level]);
nblocksx = align(nblocksx, block_align);
return nblocksx;
unsigned height, tile_height;
height = mip_minify(ptex->height0, level);
- height = util_format_get_nblocksy(ptex->format, height);
+ height = util_format_get_nblocksy(rtex->real_format, height);
tile_height = r600_get_height_alignment(screen,
rtex->array_mode[level]);
height = align(height, tile_height);
unsigned w, h, tile_height, tile_width;
tile_height = r600_get_height_alignment(screen, array_mode);
- tile_width = r600_get_block_alignment(screen, ptex->format, array_mode);
+ tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
w = mip_minify(ptex->width0, level);
h = mip_minify(ptex->height0, level);
- if (w < tile_width || h < tile_height)
+ if (w <= tile_width || h <= tile_height)
rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
else
rtex->array_mode[level] = array_mode;
unsigned array_mode)
{
struct pipe_resource *ptex = &rtex->resource.b.b.b;
- struct radeon *radeon = (struct radeon *)screen->winsys;
+ struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
enum chip_class chipc = r600_get_family_class(radeon);
unsigned size, layer_size, i, offset;
unsigned nblocksx, nblocksy;
for (i = 0, offset = 0; i <= ptex->last_level; i++) {
- unsigned blocksize = util_format_get_blocksize(ptex->format);
+ unsigned blocksize = util_format_get_blocksize(rtex->real_format);
+ unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
r600_texture_set_array_mode(screen, rtex, i, array_mode);
else
size = layer_size * 6;
}
- else
+ else if (ptex->target == PIPE_TEXTURE_3D)
size = layer_size * u_minify(ptex->depth0, i);
+ else
+ size = layer_size * ptex->array_size;
+
/* align base image and start of miptree */
if ((i == 0) || (i == 1))
- offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
+ offset = align(offset, base_align);
rtex->offset[i] = offset;
rtex->layer_size[i] = layer_size;
rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
bind = PIPE_BIND_RENDER_TARGET;
/* hackaround for S3TC */
- if (util_format_is_s3tc(res->format))
+ if (util_format_is_compressed(res->format))
return TRUE;
if (!screen->is_format_supported(screen,
res->format,
res->target,
res->nr_samples,
- bind, 0))
+ bind))
return FALSE;
if (!screen->is_format_supported(screen,
res->format,
res->target,
res->nr_samples,
- PIPE_BIND_SAMPLER_VIEW, 0))
+ PIPE_BIND_SAMPLER_VIEW))
return FALSE;
- return TRUE;
+ switch (res->usage) {
+ case PIPE_USAGE_STREAM:
+ case PIPE_USAGE_STAGING:
+ return FALSE;
+
+ default:
+ return TRUE;
+ }
}
static boolean r600_texture_get_handle(struct pipe_screen* screen,
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
struct r600_resource *resource = &rtex->resource;
- struct radeon *radeon = (struct radeon *)screen->winsys;
+ struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
return r600_bo_get_winsys_handle(radeon, resource->bo,
rtex->pitch_in_bytes[0], whandle);
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
struct r600_resource *resource = &rtex->resource;
- struct radeon *radeon = (struct radeon *)screen->winsys;
if (rtex->flushed_depth_texture)
pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
if (resource->bo) {
- r600_bo_reference(radeon, &resource->bo, NULL);
+ r600_bo_reference(&resource->bo, NULL);
}
FREE(rtex);
}
-static unsigned int r600_texture_is_referenced(struct pipe_context *context,
- struct pipe_resource *texture,
- unsigned level, int layer)
-{
- /* FIXME */
- return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
-}
-
static const struct u_resource_vtbl r600_texture_vtbl =
{
r600_texture_get_handle, /* get_handle */
r600_texture_destroy, /* resource_destroy */
- r600_texture_is_referenced, /* is_resource_referenced */
r600_texture_get_transfer, /* get_transfer */
r600_texture_transfer_destroy, /* transfer_destroy */
r600_texture_transfer_map, /* transfer_map */
unsigned array_mode,
unsigned pitch_in_bytes_override,
unsigned max_buffer_size,
- struct r600_bo *bo)
+ struct r600_bo *bo,
+ boolean alloc_bo)
{
struct r600_resource_texture *rtex;
struct r600_resource *resource;
- struct radeon *radeon = (struct radeon *)screen->winsys;
+ struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
rtex = CALLOC_STRUCT(r600_resource_texture);
if (rtex == NULL)
resource->b.b.b.screen = screen;
resource->bo = bo;
rtex->pitch_override = pitch_in_bytes_override;
+ rtex->real_format = base->format;
+
+ /* We must split depth and stencil into two separate buffers on Evergreen. */
+ if (r600_get_family_class(((struct r600_screen*)screen)->radeon) >= EVERGREEN &&
+ util_format_is_depth_and_stencil(base->format)) {
+ struct pipe_resource stencil;
+ unsigned stencil_pitch_override = 0;
+
+ switch (base->format) {
+ case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+ rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
+ break;
+ case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+ rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
+ break;
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
+ break;
+ default:
+ assert(0);
+ FREE(rtex);
+ return NULL;
+ }
+
+ /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
+ if (pitch_in_bytes_override) {
+ assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_USCALED ||
+ base->format == PIPE_FORMAT_S8_USCALED_Z24_UNORM);
+ stencil_pitch_override = pitch_in_bytes_override / 4;
+ }
+
+ /* Allocate the stencil buffer. */
+ stencil = *base;
+ stencil.format = PIPE_FORMAT_S8_USCALED;
+ rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
+ stencil_pitch_override,
+ max_buffer_size, NULL, FALSE);
+ if (!rtex->stencil) {
+ FREE(rtex);
+ return NULL;
+ }
+ /* Proceed in creating the depth buffer. */
+ }
+
/* only mark depth textures the HW can hit as depth textures */
- if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
+ if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
rtex->depth = 1;
r600_setup_miptree(screen, rtex, array_mode);
+ /* If we initialized separate stencil for Evergreen. place it after depth. */
+ if (rtex->stencil) {
+ unsigned stencil_align, stencil_offset;
+
+ stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode);
+ stencil_offset = align(rtex->size, stencil_align);
+
+ for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++)
+ rtex->stencil->offset[i] += stencil_offset;
+
+ rtex->size = stencil_offset + rtex->stencil->size;
+ }
+
resource->size = rtex->size;
- if (!resource->bo) {
+ /* Now create the backing buffer. */
+ if (!resource->bo && alloc_bo) {
struct pipe_resource *ptex = &rtex->resource.b.b.b;
- int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
+ unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
if (!resource->bo) {
+ pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
FREE(rtex);
return NULL;
}
}
+
+ if (rtex->stencil)
+ rtex->stencil->resource.bo = rtex->resource.bo;
return rtex;
}
/* Would like some magic "get_bool_option_once" routine.
*/
- if (force_tiling == -1)
- force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
+ if (force_tiling == -1) {
+#if 0
+ /* reenable when 2D tiling is fixed better */
+ struct r600_screen *rscreen = (struct r600_screen *)screen;
+ if (r600_get_minor_version(rscreen->radeon) >= 9)
+ force_tiling = debug_get_bool_option("R600_TILING", TRUE);
+#endif
+ force_tiling = debug_get_bool_option("R600_TILING", FALSE);
+ }
if (force_tiling && permit_hardware_blit(screen, templ)) {
if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
}
if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
- util_format_is_s3tc(templ->format))
+ util_format_is_compressed(templ->format))
array_mode = V_038000_ARRAY_1D_TILED_THIN1;
return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
- 0, 0, NULL);
-
+ 0, 0, NULL, TRUE);
}
static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
const struct pipe_resource *templ,
struct winsys_handle *whandle)
{
- struct radeon *rw = (struct radeon*)screen->winsys;
+ struct radeon *rw = ((struct r600_screen*)screen)->radeon;
struct r600_bo *bo = NULL;
+ unsigned stride = 0;
unsigned array_mode = 0;
/* Support only 2D textures without mipmaps */
templ->depth0 != 1 || templ->last_level != 0)
return NULL;
- bo = r600_bo_handle(rw, whandle->handle, &array_mode);
+ bo = r600_bo_handle(rw, whandle, &stride, &array_mode);
if (bo == NULL) {
return NULL;
}
return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
- whandle->stride,
- 0,
- bo);
+ stride, 0, bo, FALSE);
}
int r600_texture_depth_flush(struct pipe_context *ctx,
resource.width0 = texture->width0;
resource.height0 = texture->height0;
resource.depth0 = 1;
+ resource.array_size = 1;
resource.last_level = texture->last_level;
resource.nr_samples = 0;
resource.usage = PIPE_USAGE_DYNAMIC;
if (usage & PIPE_TRANSFER_READ) {
r600_copy_to_staging_texture(ctx, trans);
/* Always referenced in the blit. */
- ctx->flush(ctx, 0, NULL);
+ r600_flush(ctx, NULL, 0);
}
return &trans->transfer;
}
trans->transfer.stride = rtex->pitch_in_bytes[level];
+ trans->transfer.layer_stride = rtex->layer_size[level];
trans->offset = r600_texture_get_offset(rtex, level, box->z);
return &trans->transfer;
}
void* r600_texture_transfer_map(struct pipe_context *ctx,
struct pipe_transfer* transfer)
{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
struct r600_bo *bo;
enum pipe_format format = transfer->resource->format;
- struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
+ struct radeon *radeon = rctx->screen->radeon;
unsigned offset = 0;
- unsigned usage = 0;
char *map;
if (rtransfer->staging_texture) {
transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
}
- if (transfer->usage & PIPE_TRANSFER_WRITE) {
- usage |= PB_USAGE_CPU_WRITE;
-
- if (transfer->usage & PIPE_TRANSFER_DISCARD) {
- }
-
- if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
- }
- }
-
- if (transfer->usage & PIPE_TRANSFER_READ) {
- usage |= PB_USAGE_CPU_READ;
- }
-
- if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
- usage |= PB_USAGE_DONTBLOCK;
- }
-
- if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
- usage |= PB_USAGE_UNSYNCHRONIZED;
- }
-
- map = r600_bo_map(radeon, bo, usage, ctx);
- if (!map) {
+ if (!(map = r600_bo_map(radeon, bo, rctx->ctx.cs, transfer->usage))) {
return NULL;
}
struct pipe_transfer* transfer)
{
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
+ struct radeon *radeon = ((struct r600_screen*)ctx->screen)->radeon;
struct r600_bo *bo;
if (rtransfer->staging_texture) {
};
if (swizzle_view) {
- /* Combine two sets of swizzles. */
- for (i = 0; i < 4; i++) {
- swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
- swizzle_format[swizzle_view[i]] : swizzle_view[i];
- }
+ util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
} else {
memcpy(swizzle, swizzle_format, 4);
}
}
/* texture format translate */
-uint32_t r600_translate_texformat(enum pipe_format format,
+uint32_t r600_translate_texformat(struct pipe_screen *screen,
+ enum pipe_format format,
const unsigned char *swizzle_view,
uint32_t *word4_p, uint32_t *yuv_format_p)
{
uint32_t result = 0, word4 = 0, yuv_format = 0;
const struct util_format_description *desc;
boolean uniform = TRUE;
+ static int r600_enable_s3tc = -1;
+
int i;
const uint32_t sign_bit[4] = {
S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
result = FMT_8;
word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
goto out_word4;
+ case PIPE_FORMAT_Z32_FLOAT:
+ result = FMT_32_FLOAT;
+ goto out_word4;
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ result = FMT_X24_8_32_FLOAT;
+ goto out_word4;
default:
goto out_unknown;
}
case UTIL_FORMAT_COLORSPACE_SRGB:
word4 |= S_038010_FORCE_DEGAMMA(1);
- if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
- goto out_unknown; /* fails for some reason - TODO */
break;
default:
break;
}
- /* S3TC formats. TODO */
- if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
- static int r600_enable_s3tc = -1;
+ if (r600_enable_s3tc == -1) {
+ struct r600_screen *rscreen = (struct r600_screen *)screen;
+ if (r600_get_minor_version(rscreen->radeon) >= 9)
+ r600_enable_s3tc = 1;
+ else
+ r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
+ }
- if (r600_enable_s3tc == -1)
- r600_enable_s3tc =
- debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
+ if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
+ if (!r600_enable_s3tc)
+ goto out_unknown;
+
+ switch (format) {
+ case PIPE_FORMAT_RGTC1_SNORM:
+ case PIPE_FORMAT_LATC1_SNORM:
+ word4 |= sign_bit[0];
+ case PIPE_FORMAT_RGTC1_UNORM:
+ case PIPE_FORMAT_LATC1_UNORM:
+ result = FMT_BC4;
+ goto out_word4;
+ case PIPE_FORMAT_RGTC2_SNORM:
+ case PIPE_FORMAT_LATC2_SNORM:
+ word4 |= sign_bit[0] | sign_bit[1];
+ case PIPE_FORMAT_RGTC2_UNORM:
+ case PIPE_FORMAT_LATC2_UNORM:
+ result = FMT_BC5;
+ goto out_word4;
+ default:
+ goto out_unknown;
+ }
+ }
+
+ if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
if (!r600_enable_s3tc)
goto out_unknown;
}
}
+ if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
+ result = FMT_5_9_9_9_SHAREDEXP;
+ goto out_word4;
+ } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
+ result = FMT_10_11_11_FLOAT;
+ goto out_word4;
+ }
+
for (i = 0; i < desc->nr_channels; i++) {
if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
/* R8G8Bx_SNORM - TODO CxV8U8 */
- /* RGTC - TODO */
-
/* See whether the components are of the same size. */
for (i = 1; i < desc->nr_channels; i++) {
uniform = uniform && desc->channel[0].size == desc->channel[i].size;
goto out_word4;
}
}
-
+ goto out_unknown;
}
+
out_word4:
if (word4_p)
*word4_p = word4;
*yuv_format_p = yuv_format;
return result;
out_unknown:
-// R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
+ /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
return ~0;
}
projects / mesa.git / blobdiff