#include "vl/vl_mpeg12_decoder.h"
#include "r600_pipe.h"
-#include "radeon/radeon_video.h"
-#include "radeon/radeon_uvd.h"
-#include "radeon/radeon_vce.h"
+#include "radeon_video.h"
+#include "radeon_uvd.h"
+#include "radeon_vce.h"
#include "r600d.h"
#define R600_UVD_ENABLE_TILING 0
struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
struct radeon_surf* surfaces[VL_NUM_COMPONENTS] = {};
struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
- const enum pipe_format *resource_formats;
+ enum pipe_format resource_formats[3];
struct pipe_video_buffer template;
struct pipe_resource templ;
unsigned i, array_size;
assert(pipe);
/* first create the needed resources as "normal" textures */
- resource_formats = vl_video_buffer_formats(pipe->screen, tmpl->buffer_format);
- if (!resource_formats)
- return NULL;
+ vl_get_video_buffer_formats(pipe->screen, tmpl->buffer_format, resource_formats);
array_size = tmpl->interlaced ? 2 : 1;
template = *tmpl;
surfaces[i] = &resources[i]->surface;
}
- rvid_join_surfaces(ctx->b.ws, templ.bind, pbs, surfaces);
+ rvid_join_surfaces(&ctx->b, pbs, surfaces);
for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
if (!resources[i])
continue;
- /* recreate the CS handle */
- resources[i]->resource.cs_buf = ctx->b.ws->buffer_get_cs_handle(
- resources[i]->resource.buf);
+ /* reset the address */
resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address(
- resources[i]->resource.cs_buf);
+ resources[i]->resource.buf);
}
template.height *= array_size;
error:
for (i = 0; i < VL_NUM_COMPONENTS; ++i)
- pipe_resource_reference((struct pipe_resource **)&resources[i], NULL);
+ r600_texture_reference(&resources[i], NULL);
return NULL;
}
}
/* set the decoding target buffer offsets */
-static struct radeon_winsys_cs_handle* r600_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
+static struct pb_buffer* r600_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
{
struct r600_screen *rscreen = (struct r600_screen*)buf->base.context->screen;
struct r600_texture *luma = (struct r600_texture *)buf->resources[0];
struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
msg->body.decode.dt_field_mode = buf->base.interlaced;
- msg->body.decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->b.tiling_info.num_banks));
+ msg->body.decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->b.info.r600_num_banks));
ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface);
- return luma->resource.cs_buf;
+ return luma->resource.buf;
}
/* get the radeon resources for VCE */
static void r600_vce_get_buffer(struct pipe_resource *resource,
- struct radeon_winsys_cs_handle **handle,
+ struct pb_buffer **handle,
struct radeon_surf **surface)
{
struct r600_texture *res = (struct r600_texture *)resource;
if (handle)
- *handle = res->resource.cs_buf;
+ *handle = res->resource.buf;
if (surface)
*surface = &res->surface;