#define PKT3_SET_RESOURCE 0x6D
#define PKT3_SET_SAMPLER 0x6E
#define PKT3_SET_CTL_CONST 0x6F
+#define PKT3_STRMOUT_BASE_UPDATE 0x72
#define PKT3_SURFACE_BASE_UPDATE 0x73
#define SURFACE_BASE_UPDATE_DEPTH (1 << 0)
#define SURFACE_BASE_UPDATE_COLOR(x) (2 << (x))
#define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964 /* read-only */
#define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968 /* read-only */
#define R_00896C_VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x00896C /* read-only */
+#define R_008B40_PA_SC_AA_SAMPLE_LOCS_2S 0x008B40
+#define R_008B44_PA_SC_AA_SAMPLE_LOCS_4S 0x008B44
+#define R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x008B48
+#define R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x008B4C
#define R_008C00_SQ_CONFIG 0x00008C00
#define S_008C00_VC_ENABLE(x) (((x) & 0x1) << 0)
#define G_008C00_VC_ENABLE(x) (((x) >> 0) & 0x1)
#define V_0280A0_SWAP_STD_REV 0x00000002
#define V_0280A0_SWAP_ALT_REV 0x00000003
#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
+#define V_0280A0_TILE_DISABLE 0
+#define V_0280A0_CLEAR_ENABLE 1
+#define V_0280A0_FRAG_ENABLE 2
#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
#define C_0280A0_TILE_MODE 0xFFF3FFFF
#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
#define G_028808_DEGAMMA_ENABLE(x) (((x) >> 3) & 0x1)
#define C_028808_DEGAMMA_ENABLE 0xFFFFFFF7
#define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4)
+#define V_028808_NORMAL 0
+#define V_028808_DISABLE 1
#define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7)
#define C_028808_SPECIAL_OP 0xFFFFFF8F
+#define V_028808_SPECIAL_NORMAL 0x00
+#define V_028808_SPECIAL_DISABLE 0x01
+#define V_028808_SPECIAL_FAST_CLEAR 0x02
+#define V_028808_SPECIAL_FORCE_CLEAR 0x03
+#define V_028808_SPECIAL_EXPAND_COLOR 0x04
+#define V_028808_SPECIAL_EXPAND_TEXTURE 0x05
+#define V_028808_SPECIAL_EXPAND_SAMPLES 0x06
+#define V_028808_SPECIAL_RESOLVE_BOX 0x07
#define S_028808_PER_MRT_BLEND(x) (((x) & 0x1) << 7)
#define G_028808_PER_MRT_BLEND(x) (((x) >> 7) & 0x1)
#define C_028808_PER_MRT_BLEND 0xFFFFFF7F
#define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3)
#define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3)
#define C_028A40_CUT_MODE 0xFFFFFFE7
+#define R_028A6C_VGT_GS_OUT_PRIM_TYPE 0x028A6C
+#define S_028A6C_OUTPRIM_TYPE(x) (((x) & 0x3F) << 0)
+#define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
+#define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
+#define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
#define R_008040_WAIT_UNTIL 0x008040
#define S_008040_WAIT_CP_DMA_IDLE(x) (((x) & 0x1) << 8)
#define G_008040_WAIT_CP_DMA_IDLE(x) (((x) >> 8) & 0x1)
#define R_0280B4_CB_COLOR5_INFO 0x0280B4
#define R_0280B8_CB_COLOR6_INFO 0x0280B8
#define R_0280BC_CB_COLOR7_INFO 0x0280BC
+#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX 0x028C1C
+#define R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX 0x028C20
#define R_028C30_CB_CLRCMP_CONTROL 0x028C30
#define S_028C30_CLRCMP_FCN_SRC(x) (((x) & 0x7) << 0)
#define G_028C30_CLRCMP_FCN_SRC(x) (((x) >> 0) & 0x7)
#define R_0286D4_SPI_INTERP_CONTROL_0 0x0286D4
#define R_028A48_PA_SC_MPASS_PS_CNTL 0x028A48
#define R_028C00_PA_SC_LINE_CNTL 0x028C00
+#define S_028C00_EXPAND_LINE_WIDTH(x) (((x) & 0x1) << 9)
+#define G_028C00_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1)
+#define C_028C00_EXPAND_LINE_WIDTH 0xFFFFFDFF
#define S_028C00_LAST_PIXEL(x) (((x) & 0x1) << 10)
#define G_028C00_LAST_PIXEL(x) (((x) >> 10) & 0x1)
#define C_028C00_LAST_PIXEL 0xFFFFFBFF
#define S_028C08_PIX_CENTER_HALF(x) (((x) & 0x1) << 0)
#define G_028C08_PIX_CENTER_HALF(x) (((x) >> 0) & 0x1)
#define C_028C08_PIX_CENTER_HALF 0xFFFFFFFE
+#define S_028C08_QUANT_MODE(x) (((x) & 0x7) << 3)
+#define G_028C08_QUANT_MODE(x) (((x) >> 3) & 0x7)
+#define C_028C08_QUANT_MODE 0xFFFFFFC7
+#define V_028C08_X_1_16TH 0x00
+#define V_028C08_X_1_8TH 0x01
+#define V_028C08_X_1_4TH 0x02
+#define V_028C08_X_1_2 0x03
+#define V_028C08_X_1 0x04
+#define V_028C08_X_1_256TH 0x05
#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX 0x028C1C
#define R_028C48_PA_SC_AA_MASK 0x028C48
#define R_028810_PA_CL_CLIP_CNTL 0x028810
#define R_028D2C_DB_SRESULTS_COMPARE_STATE1 0x028D2C
#define R_028D30_DB_PRELOAD_CONTROL 0x028D30
#define R_028D44_DB_ALPHA_TO_MASK 0x028D44
+#define S_028D44_ALPHA_TO_MASK_ENABLE(x) (((x) & 0x1) << 0)
+#define S_028D44_ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x3) << 8)
+#define S_028D44_ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x3) << 10)
+#define S_028D44_ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x3) << 12)
+#define S_028D44_ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x3) << 14)
+#define S_028D44_OFFSET_ROUND(x) (((x) & 0x1) << 16)
#define R_028868_SQ_PGM_RESOURCES_VS 0x028868
#define R_0286CC_SPI_PS_IN_CONTROL_0 0x0286CC
#define R_0286D0_SPI_PS_IN_CONTROL_1 0x0286D0
#define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14)
#define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1)
#define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF
+/* r600 only start */
#define S_0085F0_CR_DEST_BASE_ENA(x) (((x) & 0x1) << 15)
#define G_0085F0_CR_DEST_BASE_ENA(x) (((x) >> 15) & 0x1)
#define C_0085F0_CR_DEST_BASE_ENA 0xFFFF7FFF
+/* r600 only end */
+/* evergreen only start */
+#define S_0085F0_CB8_DEST_BASE_ENA(x) (((x) & 0x1) << 15)
+#define G_0085F0_CB8_DEST_BASE_ENA(x) (((x) >> 15) & 0x1)
+#define S_0085F0_CB9_DEST_BASE_ENA(x) (((x) & 0x1) << 16)
+#define G_0085F0_CB9_DEST_BASE_ENA(x) (((x) >> 16) & 0x1)
+#define S_0085F0_CB10_DEST_BASE_ENA(x) (((x) & 0x1) << 17)
+#define G_0085F0_CB10_DEST_BASE_ENA(x) (((x) >> 17) & 0x1)
+#define S_0085F0_CB11_DEST_BASE_ENA(x) (((x) & 0x1) << 18)
+#define G_0085F0_CB11_DEST_BASE_ENA(x) (((x) >> 18) & 0x1)
+/* evergreen only end */
#define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23)
#define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1)
#define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF
#define R_028144_ALU_CONST_BUFFER_SIZE_PS_1 0x00028144
#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0 0x00028180
#define R_028184_ALU_CONST_BUFFER_SIZE_VS_1 0x00028184
+#define R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0 0x000281C0
#define R_028940_ALU_CONST_CACHE_PS_0 0x00028940
#define R_028944_ALU_CONST_CACHE_PS_1 0x00028944
#define R_028980_ALU_CONST_CACHE_VS_0 0x00028980
#define R_028984_ALU_CONST_CACHE_VS_1 0x00028984
+#define R_0289C0_ALU_CONST_CACHE_GS_0 0x000289C0
#define R_03CFF0_SQ_VTX_BASE_VTX_LOC 0x03CFF0
#define R_03CFF4_SQ_VTX_START_INST_LOC 0x03CFF4
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