r600g: set correct pitch/offset for depth textures in flushed state.

[mesa.git] / src / gallium / drivers / r600 / r700_asm.c

diff --git a/src/gallium/drivers/r600/r700_asm.c b/src/gallium/drivers/r600/r700_asm.c
index aaeaff596360ba99b94d03dec9c863cf3bb736a5..a7f2f54736e9f39d25cacfe5b86de421d2e39de5 100644 (file)
--- a/src/gallium/drivers/r600/r700_asm.c
+++ b/src/gallium/drivers/r600/r700_asm.c
@@ -20,22 +20,21 @@
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
-#include "r600_asm.h"
-#include "r600_context.h"
+#include <stdio.h>
 #include "util/u_memory.h"
+#include "r600_pipe.h"
+#include "r600_asm.h"
 #include "r700_sq.h"
-#include <stdio.h>
+
 
 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
 {
-       unsigned i;
-
        bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
                S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
                S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
                S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
                S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
-               S_SQ_ALU_WORD0_SRC0_REL(alu->src[1].rel) |
+               S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
                S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
                S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
                S_SQ_ALU_WORD0_LAST(alu->last);
@@ -51,7 +50,7 @@ int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
                                        S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
                                        S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
                                        S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
-                                       S_SQ_ALU_WORD1_BANK_SWIZZLE(0);
+                                       S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
        } else {
                bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
                                        S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
@@ -60,18 +59,11 @@ int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
                                        S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
                                        S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
                                        S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
+                                       S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
                                        S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
-                                       S_SQ_ALU_WORD1_BANK_SWIZZLE(0) |
+                                       S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
                                        S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
                                        S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
        }
-       if (alu->last) {
-               if (alu->nliteral && !alu->literal_added) {
-                       R600_ERR("Bug in ALU processing for instruction 0x%08x, literal not added correctly\n", alu->inst);
-               }
-               for (i = 0; i < alu->nliteral; i++) {
-                       bc->bytecode[id++] = alu->value[i];
-               }
-       }
        return 0;
 }