r600/sfn: Add support for reading cube image array dim.

[mesa.git] / src / gallium / drivers / r600 / sfn / sfn_shader_base.cpp

diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp
index 57053efc49abfabc5a019a966a4279b129b09722..a1a258c8cbd01d648b1e5ca96f8103b710d58e42 100644 (file)
--- a/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp
+++ b/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp
@@ -59,7 +59,8 @@ using namespace std;
 ShaderFromNirProcessor::ShaderFromNirProcessor(pipe_shader_type ptype,
                                                r600_pipe_shader_selector& sel,
                                                r600_shader &sh_info, int scratch_size,
-                                               enum chip_class chip_class):
+                                               enum chip_class chip_class,
+                                               int atomic_base):
    m_processor_type(ptype),
    m_nesting_depth(0),
    m_block_number(0),
@@ -72,9 +73,12 @@ ShaderFromNirProcessor::ShaderFromNirProcessor(pipe_shader_type ptype,
    m_pending_else(nullptr),
    m_scratch_size(scratch_size),
    m_next_hwatomic_loc(0),
-   m_sel(sel)
+   m_sel(sel),
+   m_atomic_base(atomic_base)
+
 {
    m_sh_info.processor_type = ptype;
+
 }
 
 
@@ -89,6 +93,48 @@ bool ShaderFromNirProcessor::scan_instruction(nir_instr *instr)
       nir_tex_instr *t = nir_instr_as_tex(instr);
       if (t->sampler_dim == GLSL_SAMPLER_DIM_BUF)
          sh_info().uses_tex_buffers = true;
+      if (t->op == nir_texop_txs &&
+          t->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
+          t->is_array)
+         sh_info().has_txq_cube_array_z_comp = true;
+      break;
+   }
+   case nir_instr_type_intrinsic: {
+      auto *i = nir_instr_as_intrinsic(instr);
+      switch (i->intrinsic) {
+      case nir_intrinsic_ssbo_atomic_add:
+      case nir_intrinsic_image_atomic_add:
+      case nir_intrinsic_ssbo_atomic_and:
+      case nir_intrinsic_image_atomic_and:
+      case nir_intrinsic_ssbo_atomic_or:
+      case nir_intrinsic_image_atomic_or:
+      case nir_intrinsic_ssbo_atomic_imin:
+      case nir_intrinsic_image_atomic_imin:
+      case nir_intrinsic_ssbo_atomic_imax:
+      case nir_intrinsic_image_atomic_imax:
+      case nir_intrinsic_ssbo_atomic_umin:
+      case nir_intrinsic_image_atomic_umin:
+      case nir_intrinsic_ssbo_atomic_umax:
+      case nir_intrinsic_image_atomic_umax:
+      case nir_intrinsic_image_atomic_xor:
+      case nir_intrinsic_image_atomic_exchange:
+      case nir_intrinsic_image_atomic_comp_swap:
+         m_sel.info.writes_memory = 1;
+         /* fallthrough */
+      case nir_intrinsic_image_load:
+         m_ssbo_instr.set_require_rat_return_address();
+         break;
+      case nir_intrinsic_image_size: {
+         if (nir_intrinsic_image_dim(i) == GLSL_SAMPLER_DIM_CUBE &&
+             nir_intrinsic_image_array(i) && nir_dest_num_components(i->dest) > 2)
+            sh_info().has_txq_cube_array_z_comp = true;
+      }
+
+      default:
+         ;
+      }
+
+
    }
    default:
       ;
@@ -198,7 +244,7 @@ bool ShaderFromNirProcessor::process_uniforms(nir_variable *uniform)
       struct r600_shader_atomic& atom = sh_info().atomics[sh_info().nhwatomic_ranges];
       ++sh_info().nhwatomic_ranges;
       atom.buffer_id = uniform->data.binding;
-      atom.hw_idx = m_next_hwatomic_loc;
+      atom.hw_idx = m_atomic_base + m_next_hwatomic_loc;
       atom.start = m_next_hwatomic_loc;
       atom.end = atom.start + natomics - 1;
       m_next_hwatomic_loc = atom.end + 1;
@@ -486,6 +532,11 @@ bool ShaderFromNirProcessor::emit_intrinsic_instruction(nir_intrinsic_instr* ins
    if (emit_intrinsic_instruction_override(instr))
       return true;
 
+   if (m_ssbo_instr.emit(&instr->instr)) {
+      m_sel.info.writes_memory = true;
+      return true;
+   }
+
    switch (instr->intrinsic) {
    case nir_intrinsic_load_deref: {
       auto var = get_deref_location(instr->src[0]);
@@ -520,39 +571,24 @@ bool ShaderFromNirProcessor::emit_intrinsic_instruction(nir_intrinsic_instr* ins
       return emit_discard_if(instr);
    case nir_intrinsic_load_ubo_r600:
       return emit_load_ubo(instr);
-   case nir_intrinsic_atomic_counter_add:
-   case nir_intrinsic_atomic_counter_and:
-   case nir_intrinsic_atomic_counter_exchange:
-   case nir_intrinsic_atomic_counter_max:
-   case nir_intrinsic_atomic_counter_min:
-   case nir_intrinsic_atomic_counter_or:
-   case nir_intrinsic_atomic_counter_xor:
-   case nir_intrinsic_atomic_counter_comp_swap:
-   case nir_intrinsic_atomic_counter_read:
-   case nir_intrinsic_atomic_counter_post_dec:
-   case nir_intrinsic_atomic_counter_inc:
-   case nir_intrinsic_atomic_counter_pre_dec:
-   case nir_intrinsic_store_ssbo:
-      m_sel.info.writes_memory = true;
-      /* fallthrough */
-   case nir_intrinsic_load_ssbo:
-      return m_ssbo_instr.emit(&instr->instr);
-      break;
-   case nir_intrinsic_copy_deref:
-   case nir_intrinsic_load_constant:
-   case nir_intrinsic_load_input:
-   case nir_intrinsic_store_output:
    case nir_intrinsic_load_tcs_in_param_base_r600:
       return emit_load_tcs_param_base(instr, 0);
    case nir_intrinsic_load_tcs_out_param_base_r600:
       return emit_load_tcs_param_base(instr, 16);
    case nir_intrinsic_load_local_shared_r600:
+   case nir_intrinsic_load_shared:
       return emit_load_local_shared(instr);
    case nir_intrinsic_store_local_shared_r600:
+   case nir_intrinsic_store_shared:
       return emit_store_local_shared(instr);
    case nir_intrinsic_control_barrier:
    case nir_intrinsic_memory_barrier_tcs_patch:
+   case nir_intrinsic_memory_barrier_shared:
       return emit_barrier(instr);
+   case nir_intrinsic_copy_deref:
+   case nir_intrinsic_load_constant:
+   case nir_intrinsic_load_input:
+   case nir_intrinsic_store_output:
 
    default:
       fprintf(stderr, "r600-nir: Unsupported intrinsic %d\n", instr->intrinsic);
@@ -988,10 +1024,10 @@ void ShaderFromNirProcessor::set_input(unsigned pos, PValue var)
    m_inputs[pos] = var;
 }
 
-void ShaderFromNirProcessor::set_output(unsigned pos, PValue var)
+void ShaderFromNirProcessor::set_output(unsigned pos, int sel)
 {
-   r600::sfn_log << SfnLog::io << "Set output[" << pos << "] =" << *var <<  "\n";
-   m_outputs[pos] = var;
+   r600::sfn_log << SfnLog::io << "Set output[" << pos << "] =" << sel <<  "\n";
+   m_outputs[pos] = sel;
 }
 
 void ShaderFromNirProcessor::append_block(int nesting_change)
@@ -1008,7 +1044,7 @@ void ShaderFromNirProcessor::finalize()
       m_sh_info.input[i.first].gpr = i.second->sel();
 
    for (auto& i : m_outputs)
-      m_sh_info.output[i.first].gpr = i.second->sel();
+      m_sh_info.output[i.first].gpr = i.second;
 
    m_output.push_back(m_export_output);
 }