const r600_shader_key &key,
enum chip_class chip_class):
VertexStage(PIPE_SHADER_GEOMETRY, sel, sh->shader,
- sh->scratch_space_needed, chip_class),
+ sh->scratch_space_needed, chip_class, key.gs.first_atomic_counter),
m_pipe_shader(sh),
m_so_info(&sel.so),
m_first_vertex_emitted(false),
auto ir = new MemRingOutIntruction(cf_mem_ring, mem_write_ind, out_value,
4 * out_var->data.driver_location,
instr->num_components, m_export_base);
- emit_instruction(ir);
+
+ streamout_data[out_var->data.location] = ir;
return true;
}
input->data.location == VARYING_SLOT_COL1 ||
input->data.location == VARYING_SLOT_BFC0 ||
input->data.location == VARYING_SLOT_BFC1 ||
+ input->data.location == VARYING_SLOT_PNTC ||
(input->data.location >= VARYING_SLOT_VAR0 &&
input->data.location <= VARYING_SLOT_VAR31) ||
(input->data.location >= VARYING_SLOT_TEX0 &&
output->data.location <= VARYING_SLOT_TEX7) ||
output->data.location == VARYING_SLOT_BFC0 ||
output->data.location == VARYING_SLOT_BFC1 ||
+ output->data.location == VARYING_SLOT_PNTC ||
output->data.location == VARYING_SLOT_CLIP_VERTEX ||
output->data.location == VARYING_SLOT_CLIP_DIST0 ||
output->data.location == VARYING_SLOT_CLIP_DIST1 ||
int stream = nir_intrinsic_stream_id(instr);
assert(stream < 4);
+ for(auto v: streamout_data) {
+ if (stream == 0 || v.first != VARYING_SLOT_POS) {
+ v.second->patch_ring(stream);
+ emit_instruction(v.second);
+ } else
+ delete v.second;
+ }
+ streamout_data.clear();
emit_instruction(new EmitVertex(stream, cut));
if (!cut)