radeon/llvm: Lower loads from USE_SGPR adddress space during DAG lowering

[mesa.git] / src / gallium / drivers / radeon / AMDGPUISelLowering.cpp

diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 2e6782840f2161b904f174ccce34b0645ff1d0d9..e22df8efb0efdbe4f6fee82f38b83fa89fa98e9c 100644 (file)
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -311,13 +311,6 @@ bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const
   return false;
 }
 
-void AMDGPUTargetLowering::addLiveIn(MachineInstr * MI,
-    MachineFunction * MF, MachineRegisterInfo & MRI,
-    const TargetInstrInfo * TII, unsigned reg) const
-{
-  AMDGPU::utilAddLiveIn(MF, MRI, TII, reg, MI->getOperand(0).getReg());
-}
-
 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
                                                   const TargetRegisterClass *RC,
                                                    unsigned Reg, EVT VT) const {