radeon/llvm: Move lowering of SETCC node to R600ISelLowering

[mesa.git] / src / gallium / drivers / radeon / AMDGPUInstrInfo.h

diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
index fa009bc6302a890d49efe4cdc9157820af27cfa6..e6b79c867a84709ac967b4a9d977a4eff5534b25 100644 (file)
--- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
@@ -1,4 +1,4 @@
-//===-- AMDGPUInstrInfo.h - TODO: Add brief description -------===//
+//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -7,7 +7,8 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// TODO: Add full description
+// This file contains the definition of a TargetInstrInfo class that is common
+// to all AMD GPUs.
 //
 //===----------------------------------------------------------------------===//
 
@@ -21,39 +22,27 @@
 
 namespace llvm {
 
-  class AMDGPUTargetMachine;
-  class MachineFunction;
-  class MachineInstr;
-  class MachineInstrBuilder;
+class AMDGPUTargetMachine;
+class MachineFunction;
+class MachineInstr;
+class MachineInstrBuilder;
 
-  class AMDGPUInstrInfo : public AMDILInstrInfo {
-  private:
+class AMDGPUInstrInfo : public AMDILInstrInfo {
+private:
   AMDGPUTargetMachine & TM;
-  std::map<unsigned, unsigned> amdilToISA;
 
-  public:
+public:
   explicit AMDGPUInstrInfo(AMDGPUTargetMachine &tm);
 
   virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
 
-  virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
-
+  /// convertToISA - Convert the AMDIL MachineInstr to a supported ISA
+  /// MachineInstr
   virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
     DebugLoc DL) const;
 
-  bool isRegPreload(const MachineInstr &MI) const;
-
-  #include "AMDGPUInstrEnums.h.include"
-  };
+};
 
 } // End llvm namespace
 
-/* AMDGPU target flags are stored in bits 32-39 */
-namespace AMDGPU_TFLAG_SHIFTS {
-  enum TFLAGS {
-    PRELOAD_REG = 32
-  };
-}
-
-
 #endif // AMDGPUINSTRINFO_H_