radeon/llvm: Disable SI flow control again for now.

[mesa.git] / src / gallium / drivers / radeon / AMDGPUTargetMachine.cpp

diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
index 5046418b0ec22d09f77c61c03499a06ae9df8c57..bfe9d81303baaeaf040d2c01d60381b9b9a5c031 100644 (file)
--- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp
@@ -14,10 +14,8 @@
 
 #include "AMDGPUTargetMachine.h"
 #include "AMDGPU.h"
-#include "AMDILTargetMachine.h"
 #include "R600ISelLowering.h"
 #include "R600InstrInfo.h"
-#include "R600KernelParameters.h"
 #include "SIISelLowering.h"
 #include "SIInstrInfo.h"
 #include "llvm/Analysis/Passes.h"
@@ -31,9 +29,15 @@
 #include "llvm/Support/raw_os_ostream.h"
 #include "llvm/Transforms/IPO.h"
 #include "llvm/Transforms/Scalar.h"
+#include <llvm/CodeGen/Passes.h>
 
 using namespace llvm;
 
+extern "C" void LLVMInitializeAMDGPUTarget() {
+  // Register the target
+  RegisterTargetMachine<AMDGPUTargetMachine> X(TheAMDGPUTarget);
+}
+
 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
     StringRef CPU, StringRef FS,
   TargetOptions Options,
@@ -41,13 +45,18 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
   CodeGenOpt::Level OptLevel
 )
 :
-  AMDILTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
+  LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
   Subtarget(TT, CPU, FS),
+  DataLayout(Subtarget.getDataLayout()),
+  FrameLowering(TargetFrameLowering::StackGrowsUp,
+      Subtarget.device()->getStackAlignment(), 0),
+  IntrinsicInfo(this),
+  InstrItins(&Subtarget.getInstrItineraryData()),
   mDump(false)
 
 {
-  /* TLInfo uses InstrInfo so it must be initialized after. */
-  if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
+  // TLInfo uses InstrInfo so it must be initialized after.
+  if (Subtarget.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
     InstrInfo = new R600InstrInfo(*this);
     TLInfo = new R600TargetLowering(*this);
   } else {
@@ -60,31 +69,6 @@ AMDGPUTargetMachine::~AMDGPUTargetMachine()
 {
 }
 
-bool AMDGPUTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
-                                              formatted_raw_ostream &Out,
-                                              CodeGenFileType FileType,
-                                              bool DisableVerify) {
-  /* XXX: Hack here addPassesToEmitFile will fail, but this is Ok since we are
-   * only using it to access addPassesToGenerateCode() */
-  bool fail = LLVMTargetMachine::addPassesToEmitFile(PM, Out, FileType,
-                                                     DisableVerify);
-  assert(fail);
-
-  const AMDILSubtarget &STM = getSubtarget<AMDILSubtarget>();
-  std::string gpu = STM.getDeviceName();
-  if (gpu == "SI") {
-    PM.add(createSICodeEmitterPass(Out));
-  } else if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
-    PM.add(createR600CodeEmitterPass(Out));
-  } else {
-    abort();
-    return true;
-  }
-  PM.add(createGCInfoDeleter());
-
-  return false;
-}
-
 namespace {
 class AMDGPUPassConfig : public TargetPassConfig {
 public:
@@ -111,30 +95,21 @@ TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
 bool
 AMDGPUPassConfig::addPreISel()
 {
-  const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
-  if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
-    PM->add(createR600KernelParametersPass(
-                     getAMDGPUTargetMachine().getTargetData()));
-  }
   return false;
 }
 
 bool AMDGPUPassConfig::addInstSelector() {
-  PM->add(createAMDILPeepholeOpt(*TM));
-  PM->add(createAMDILISelDag(getAMDGPUTargetMachine()));
+  PM->add(createAMDGPUPeepholeOpt(*TM));
+  PM->add(createAMDGPUISelDag(getAMDGPUTargetMachine()));
   return false;
 }
 
 bool AMDGPUPassConfig::addPreRegAlloc() {
-  const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
+  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
 
-  if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
-    PM->add(createR600LowerInstructionsPass(*TM));
-  } else {
-    PM->add(createSILowerShaderInstructionsPass(*TM));
+  if (ST.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
     PM->add(createSIAssignInterpRegsPass(*TM));
   }
-  PM->add(createAMDGPULowerInstructionsPass(*TM));
   PM->add(createAMDGPUConvertToISAPass(*TM));
   return false;
 }
@@ -144,15 +119,23 @@ bool AMDGPUPassConfig::addPostRegAlloc() {
 }
 
 bool AMDGPUPassConfig::addPreSched2() {
+
+  addPass(IfConverterID);
   return false;
 }
 
 bool AMDGPUPassConfig::addPreEmitPass() {
-  const AMDILSubtarget &ST = TM->getSubtarget<AMDILSubtarget>();
-  PM->add(createAMDILCFGPreparationPass(*TM));
-  PM->add(createAMDILCFGStructurizerPass(*TM));
-  if (ST.device()->getGeneration() == AMDILDeviceInfo::HD7XXX) {
-    PM->add(createSIPropagateImmReadsPass(*TM));
+  PM->add(createAMDGPUCFGPreparationPass(*TM));
+  PM->add(createAMDGPUCFGStructurizerPass(*TM));
+
+  const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>();
+  if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
+    PM->add(createR600ExpandSpecialInstrsPass(*TM));
+    addPass(FinalizeMachineBundlesID);
+  } else {
+    PM->add(createSILowerLiteralConstantsPass(*TM));
+    // piglit is unreliable (VM protection faults, GPU lockups) with this pass:
+    //PM->add(createSILowerFlowControlPass(*TM));
   }
 
   return false;