radeon/llvm: fix calculation of max register number

[mesa.git] / src / gallium / drivers / radeon / AMDGPUTargetMachine.h

diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.h b/src/gallium/drivers/radeon/AMDGPUTargetMachine.h
index 2428fe638a731e14078ec162be4587b2b51b3657..7c51ca50a3dea763af5b644665286761b30e60d0 100644 (file)
--- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.h
+++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.h
@@ -15,7 +15,9 @@
 #define AMDGPU_TARGET_MACHINE_H
 
 #include "AMDGPUInstrInfo.h"
-#include "AMDILTargetMachine.h"
+#include "AMDGPUSubtarget.h"
+#include "AMDILFrameLowering.h"
+#include "AMDILIntrinsicInfo.h"
 #include "R600ISelLowering.h"
 #include "llvm/ADT/OwningPtr.h"
 #include "llvm/Target/TargetData.h"
@@ -24,13 +26,16 @@ namespace llvm {
 
 MCAsmInfo* createMCAsmInfo(const Target &T, StringRef TT);
 
-class AMDGPUTargetMachine : public AMDILTargetMachine {
-  AMDILSubtarget Subtarget;
-     const AMDGPUInstrInfo * InstrInfo;
-     AMDGPUTargetLowering * TLInfo;
-     AMDILGlobalManager *mGM;
-     AMDILKernelManager *mKM;
-     bool mDump;
+class AMDGPUTargetMachine : public LLVMTargetMachine {
+
+  AMDGPUSubtarget Subtarget;
+  const TargetData DataLayout;
+  AMDGPUFrameLowering FrameLowering;
+  AMDGPUIntrinsicInfo IntrinsicInfo;
+  const AMDGPUInstrInfo * InstrInfo;
+  AMDGPUTargetLowering * TLInfo;
+  const InstrItineraryData* InstrItins;
+  bool mDump;
 
 public:
    AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS,
@@ -39,14 +44,24 @@ public:
                        Reloc::Model RM, CodeModel::Model CM,
                        CodeGenOpt::Level OL);
    ~AMDGPUTargetMachine();
+   virtual const AMDGPUFrameLowering* getFrameLowering() const {
+     return &FrameLowering;
+   }
+   virtual const AMDGPUIntrinsicInfo* getIntrinsicInfo() const {
+     return &IntrinsicInfo;
+   }
    virtual const AMDGPUInstrInfo *getInstrInfo() const {return InstrInfo;}
-   virtual const AMDILSubtarget *getSubtargetImpl() const {return &Subtarget; }
+   virtual const AMDGPUSubtarget *getSubtargetImpl() const {return &Subtarget; }
    virtual const AMDGPURegisterInfo *getRegisterInfo() const {
       return &InstrInfo->getRegisterInfo();
    }
    virtual AMDGPUTargetLowering * getTargetLowering() const {
       return TLInfo;
    }
+   virtual const InstrItineraryData* getInstrItineraryData() const {
+      return InstrItins;
+   }
+   virtual const TargetData* getTargetData() const { return &DataLayout; }
    virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
    virtual bool addPassesToEmitFile(PassManagerBase &PM,
                                               formatted_raw_ostream &Out,
@@ -54,6 +69,6 @@ public:
                                               bool DisableVerify);
 };
 
-} /* End namespace llvm */
+} // End namespace llvm
 
-#endif /* AMDGPU_TARGET_MACHINE_H */
+#endif // AMDGPU_TARGET_MACHINE_H