radeon/llvm: Move lowering of SETCC node to R600ISelLowering

[mesa.git] / src / gallium / drivers / radeon / AMDGPUUtil.cpp

diff --git a/src/gallium/drivers/radeon/AMDGPUUtil.cpp b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
index 6fb01b687f3c16873d2e0873420e4f6fbc9d753c..63b359ffc145a16eb0b399485f42f01ce3d46083 100644 (file)
--- a/src/gallium/drivers/radeon/AMDGPUUtil.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUUtil.cpp
@@ -1,4 +1,4 @@
-//===-- AMDGPUUtil.cpp - TODO: Add brief description -------===//
+//===-- AMDGPUUtil.cpp - AMDGPU Utility functions -------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -7,120 +7,132 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// TODO: Add full description
+// Common utility functions used by hw codegen targets
 //
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUUtil.h"
 #include "AMDGPURegisterInfo.h"
 #include "AMDIL.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 
 using namespace llvm;
 
-/* Some instructions act as place holders to emulate operations that the GPU
- * hardware does automatically. This function can be used to check if
- * an opcode falls into this category. */
-bool llvm::isPlaceHolderOpcode(unsigned opcode)
+// Some instructions act as place holders to emulate operations that the GPU
+// hardware does automatically. This function can be used to check if
+// an opcode falls into this category.
+bool AMDGPU::isPlaceHolderOpcode(unsigned opcode)
 {
   switch (opcode) {
   default: return false;
-  case AMDIL::EXPORT_REG:
-  case AMDIL::RETURN:
-  case AMDIL::LOAD_INPUT:
-  case AMDIL::LAST:
-  case AMDIL::MASK_WRITE:
-  case AMDIL::RESERVE_REG:
+  case AMDGPU::RETURN:
+  case AMDGPU::LOAD_INPUT:
+  case AMDGPU::LAST:
+  case AMDGPU::MASK_WRITE:
+  case AMDGPU::RESERVE_REG:
     return true;
   }
 }
 
-bool llvm::isTransOp(unsigned opcode)
+bool AMDGPU::isTransOp(unsigned opcode)
 {
   switch(opcode) {
     default: return false;
 
-    case AMDIL::COS_f32:
-    case AMDIL::COS_r600:
-    case AMDIL::COS_eg:
-    case AMDIL::RSQ_f32:
-    case AMDIL::FTOI:
-    case AMDIL::ITOF:
-    case AMDIL::MULLIT:
-    case AMDIL::MUL_LIT_r600:
-    case AMDIL::MUL_LIT_eg:
-    case AMDIL::SHR_i32:
-    case AMDIL::SIN_f32:
-    case AMDIL::EXP_f32:
-    case AMDIL::EXP_IEEE_r600:
-    case AMDIL::EXP_IEEE_eg:
-    case AMDIL::LOG_CLAMPED_r600:
-    case AMDIL::LOG_IEEE_r600:
-    case AMDIL::LOG_CLAMPED_eg:
-    case AMDIL::LOG_IEEE_eg:
-    case AMDIL::LOG_f32:
+    case AMDGPU::COS_r600:
+    case AMDGPU::COS_eg:
+    case AMDGPU::MULLIT:
+    case AMDGPU::MUL_LIT_r600:
+    case AMDGPU::MUL_LIT_eg:
+    case AMDGPU::EXP_IEEE_r600:
+    case AMDGPU::EXP_IEEE_eg:
+    case AMDGPU::LOG_CLAMPED_r600:
+    case AMDGPU::LOG_IEEE_r600:
+    case AMDGPU::LOG_CLAMPED_eg:
+    case AMDGPU::LOG_IEEE_eg:
       return true;
   }
 }
 
-bool llvm::isTexOp(unsigned opcode)
+bool AMDGPU::isTexOp(unsigned opcode)
 {
   switch(opcode) {
   default: return false;
-  case AMDIL::TEX_SAMPLE:
-  case AMDIL::TEX_SAMPLE_C:
-  case AMDIL::TEX_SAMPLE_L:
-  case AMDIL::TEX_SAMPLE_C_L:
-  case AMDIL::TEX_SAMPLE_LB:
-  case AMDIL::TEX_SAMPLE_C_LB:
-  case AMDIL::TEX_SAMPLE_G:
-  case AMDIL::TEX_SAMPLE_C_G:
+  case AMDGPU::TEX_LD:
+  case AMDGPU::TEX_GET_TEXTURE_RESINFO:
+  case AMDGPU::TEX_SAMPLE:
+  case AMDGPU::TEX_SAMPLE_C:
+  case AMDGPU::TEX_SAMPLE_L:
+  case AMDGPU::TEX_SAMPLE_C_L:
+  case AMDGPU::TEX_SAMPLE_LB:
+  case AMDGPU::TEX_SAMPLE_C_LB:
+  case AMDGPU::TEX_SAMPLE_G:
+  case AMDGPU::TEX_SAMPLE_C_G:
+  case AMDGPU::TEX_GET_GRADIENTS_H:
+  case AMDGPU::TEX_GET_GRADIENTS_V:
+  case AMDGPU::TEX_SET_GRADIENTS_H:
+  case AMDGPU::TEX_SET_GRADIENTS_V:
     return true;
   }
 }
 
-bool llvm::isReductionOp(unsigned opcode)
+bool AMDGPU::isReductionOp(unsigned opcode)
 {
   switch(opcode) {
     default: return false;
-    case AMDIL::DOT4_r600:
-    case AMDIL::DOT4_eg:
+    case AMDGPU::DOT4_r600:
+    case AMDGPU::DOT4_eg:
       return true;
   }
 }
 
-bool llvm::isFCOp(unsigned opcode)
+bool AMDGPU::isCubeOp(unsigned opcode)
+{
+  switch(opcode) {
+    default: return false;
+    case AMDGPU::CUBE_r600:
+    case AMDGPU::CUBE_eg:
+      return true;
+  }
+}
+
+
+bool AMDGPU::isFCOp(unsigned opcode)
 {
   switch(opcode) {
   default: return false;
-  case AMDIL::BREAK_LOGICALZ_f32:
-  case AMDIL::BREAK_LOGICALNZ_i32:
-  case AMDIL::BREAK_LOGICALZ_i32:
-  case AMDIL::CONTINUE_LOGICALNZ_f32:
-  case AMDIL::IF_LOGICALNZ_i32:
-  case AMDIL::IF_LOGICALZ_f32:
-       case AMDIL::ELSE:
-  case AMDIL::ENDIF:
-  case AMDIL::ENDLOOP:
-  case AMDIL::IF_LOGICALNZ_f32:
-  case AMDIL::WHILELOOP:
+  case AMDGPU::BREAK_LOGICALZ_f32:
+  case AMDGPU::BREAK_LOGICALNZ_i32:
+  case AMDGPU::BREAK_LOGICALZ_i32:
+  case AMDGPU::BREAK_LOGICALNZ_f32:
+  case AMDGPU::CONTINUE_LOGICALNZ_f32:
+  case AMDGPU::IF_LOGICALNZ_i32:
+  case AMDGPU::IF_LOGICALZ_f32:
+  case AMDGPU::ELSE:
+  case AMDGPU::ENDIF:
+  case AMDGPU::ENDLOOP:
+  case AMDGPU::IF_LOGICALNZ_f32:
+  case AMDGPU::WHILELOOP:
     return true;
   }
 }
 
-void AMDGPU::utilAddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
-    const struct TargetInstrInfo * TII, unsigned physReg, unsigned virtReg)
+void AMDGPU::utilAddLiveIn(MachineFunction * MF,
+                           MachineRegisterInfo & MRI,
+                           const TargetInstrInfo * TII,
+                           unsigned physReg, unsigned virtReg)
 {
     if (!MRI.isLiveIn(physReg)) {
       MRI.addLiveIn(physReg, virtReg);
+      MF->front().addLiveIn(physReg);
       BuildMI(MF->front(), MF->front().begin(), DebugLoc(),
-                           TII->get(TargetOpcode::COPY), virtReg)
-            .addReg(physReg);
+              TII->get(TargetOpcode::COPY), virtReg)
+                .addReg(physReg);
     } else {
       MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg));
     }