radeon/llvm: Move lowering of SETCC node to R600ISelLowering

[mesa.git] / src / gallium / drivers / radeon / AMDILInstrInfo.h

diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.h b/src/gallium/drivers/radeon/AMDILInstrInfo.h
index 9de16ed8e59165c7b8846eaba6c2c42f62bff65f..bff729b4685832073ec3b4ecc68880c6f811b1ae 100644 (file)
--- a/src/gallium/drivers/radeon/AMDILInstrInfo.h
+++ b/src/gallium/drivers/radeon/AMDILInstrInfo.h
@@ -18,7 +18,7 @@
 #include "llvm/Target/TargetInstrInfo.h"
 
 #define GET_INSTRINFO_HEADER
-#include "AMDILGenInstrInfo.inc"
+#include "AMDGPUGenInstrInfo.inc"
 
 namespace llvm {
   // AMDIL - This namespace holds all of the target specific flags that
@@ -77,7 +77,7 @@ public:
   virtual void copyPhysReg(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI, DebugLoc DL,
                            unsigned DestReg, unsigned SrcReg,
-                           bool KillSrc) const;
+                           bool KillSrc) const = 0;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI,
@@ -147,6 +147,13 @@ public:
   bool isLocalAtomic(llvm::MachineInstr *MI) const;
   bool isGlobalAtomic(llvm::MachineInstr *MI) const;
   bool isArenaAtomic(llvm::MachineInstr *MI) const;
+
+  virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
+                                        int64_t Imm) const = 0;
+
+  virtual unsigned getIEQOpcode() const = 0;
+
+  virtual bool isMov(unsigned Opcode) const = 0;
 };
 
 }