radeon/llvm: Use correct float->int conversion opcode on SI.

[mesa.git] / src / gallium / drivers / radeon / AMDILInstrInfo.td

diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.td b/src/gallium/drivers/radeon/AMDILInstrInfo.td
index 5947192048e97f3884326f30b890cfe7234f464c..779566d4bf37a366e58249e6ba1482947d3e5a73 100644 (file)
--- a/src/gallium/drivers/radeon/AMDILInstrInfo.td
+++ b/src/gallium/drivers/radeon/AMDILInstrInfo.td
@@ -115,7 +115,6 @@ def IL_retflag       : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
 // Instructions
 //===--------------------------------------------------------------------===//
 // Floating point math functions
-def IL_cmov_logical : SDNode<"AMDGPUISD::CMOVLOG", SDTIL_GenTernaryOp>;
 def IL_div_inf      : SDNode<"AMDGPUISD::DIV_INF", SDTIL_GenBinaryOp>;
 def IL_mad          : SDNode<"AMDGPUISD::MAD", SDTIL_GenTernaryOp>;
 
@@ -218,19 +217,12 @@ include "AMDILIntrinsics.td"
 // Custom Inserter for Branches and returns, this eventually will be a
 // seperate pass
 //===---------------------------------------------------------------------===//
-let isTerminator = 1 in {
+let isTerminator = 1, usesCustomInserter = 1 in {
   def BRANCH : ILFormat<(outs), (ins brtarget:$target),
       "; Pseudo unconditional branch instruction",
       [(br bb:$target)]>;
   defm BRANCH_COND : BranchConditional<IL_brcond>;
 }
-//===---------------------------------------------------------------------===//
-// return instructions
-//===---------------------------------------------------------------------===//
-let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
-  def RETURN          : ILFormat<(outs), (ins variable_ops),
-      "RETURN", [(IL_retflag)]>;
-}
 
 //===---------------------------------------------------------------------===//
 // Flow and Program control Instructions