radeonsi: Handle position input parameter for pixel shaders v2

[mesa.git] / src / gallium / drivers / radeon / MCTargetDesc / R600MCCodeEmitter.cpp

diff --git a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
index 46360e3ccbd79b5086e44c75b263331c312ae686..34c4b396c7796448d3e52a4194e306fe64fa09df 100644 (file)
--- a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -149,12 +149,6 @@ MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
 
 void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                                        SmallVectorImpl<MCFixup> &Fixups) const {
-/*
-  if (MI.getNumOperands() > 1 && MI.getOperand(0).isReg() &&
-      MI.getOperand(0).isDead()) {
-    return;
-  }
-*/
   if (isTexOp(MI.getOpcode())) {
     EmitTexInstr(MI, Fixups, OS);
   } else if (isFCOp(MI.getOpcode())){
@@ -168,8 +162,6 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
     case AMDGPU::RAT_WRITE_CACHELESS_eg:
       {
         uint64_t inst = getBinaryCodeForInstr(MI, Fixups);
-        // XXX: Set End Of Program bit when necessary
-        //  inst |= (((uint64_t)1) << 53);
         EmitByte(INSTR_NATIVE, OS);
         Emit(inst, OS);
         break;
@@ -209,12 +201,6 @@ void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI,
   if (GET_FLAG_OPERAND_IDX(MCDesc.TSFlags) != 0)
     NumOperands--;
 
-   // Some instructions are just place holder instructions that represent
-   // operations that the GPU does automatically.  They should be ignored.
-//  if (TII->isPlaceHolderOpcode(MI.getOpcode())) {
-//    return;
-//  }
-
   if(MI.getOpcode() == AMDGPU::PRED_X)
     NumOperands = 2;