+C_SOURCES := \
+ radeon_uvd.c
-GENERATED_SOURCES := \
- R600ShaderPatterns.td \
- R600RegisterInfo.td \
- AMDGPUInstrEnums.td \
- SIRegisterInfo.td \
- SIRegisterGetHWRegNum.inc \
- AMDILGenRegisterInfo.inc \
- AMDILGenInstrInfo.inc \
- AMDILGenAsmWriter.inc \
- AMDILGenDAGISel.inc \
- AMDILGenCallingConv.inc \
- AMDILGenSubtargetInfo.inc \
- AMDILGenEDInfo.inc \
- AMDILGenIntrinsics.inc \
- AMDILGenCodeEmitter.inc \
- AMDGPUInstrEnums.h.include \
- AMDGPUInstrEnums.include
-
-CPP_SOURCES := \
- AMDIL7XXDevice.cpp \
- AMDILCFGStructurizer.cpp \
- AMDILDevice.cpp \
- AMDILDeviceInfo.cpp \
- AMDILEvergreenDevice.cpp \
- AMDILELFWriterInfo.cpp \
- AMDILFrameLowering.cpp \
- AMDILInstrInfo.cpp \
- AMDILIntrinsicInfo.cpp \
- AMDILISelDAGToDAG.cpp \
- AMDILISelLowering.cpp \
- AMDILLiteralManager.cpp \
- AMDILMachineFunctionInfo.cpp \
- AMDILMachinePeephole.cpp \
- AMDILMCCodeEmitter.cpp \
- AMDILModuleInfo.cpp \
- AMDILNIDevice.cpp \
- AMDILPeepholeOptimizer.cpp \
- AMDILRegisterInfo.cpp \
- AMDILSIDevice.cpp \
- AMDILSubtarget.cpp \
- AMDILTargetMachine.cpp \
- AMDILUtilityFunctions.cpp \
- AMDGPUTargetMachine.cpp \
- AMDGPUISelLowering.cpp \
- AMDGPUConvertToISA.cpp \
- AMDGPULowerInstructions.cpp \
- AMDGPULowerShaderInstructions.cpp \
- AMDGPUReorderPreloadInstructions.cpp \
- AMDGPUInstrInfo.cpp \
- AMDGPURegisterInfo.cpp \
- AMDGPUUtil.cpp \
- R600CodeEmitter.cpp \
- R600ISelLowering.cpp \
- R600InstrInfo.cpp \
- R600KernelParameters.cpp \
- R600LowerInstructions.cpp \
- R600LowerShaderInstructions.cpp \
- R600RegisterInfo.cpp \
- SIAssignInterpRegs.cpp \
- SICodeEmitter.cpp \
- SIInstrInfo.cpp \
- SIISelLowering.cpp \
- SILowerShaderInstructions.cpp \
- SIMachineFunctionInfo.cpp \
- SIPropagateImmReads.cpp \
- SIRegisterInfo.cpp \
- MCTargetDesc/AMDILMCAsmInfo.cpp \
- MCTargetDesc/AMDILMCTargetDesc.cpp \
- TargetInfo/AMDILTargetInfo.cpp \
+LLVM_CPP_FILES := \
radeon_llvm_emit.cpp
-C_SOURCES := \
- radeon_setup_tgsi_llvm.c
+LLVM_C_FILES := \
+ radeon_setup_tgsi_llvm.c \
+ radeon_llvm_util.c