radeon/uvd: enable interlaced buffers by default

[mesa.git] / src / gallium / drivers / radeon / Makefile.sources

diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources
index b7f70c2dad5453adda15300aa5656dc96b8738f5..a23d5c4ad2c7b4d179b6c10c4145617fe0f1ab54 100644 (file)
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -1,66 +1,9 @@
+C_SOURCES := \
+       radeon_uvd.c
 
-GENERATED_SOURCES := \
-       R600Intrinsics.td               \
-       R600RegisterInfo.td             \
-       AMDGPUInstrEnums.td             \
-       SIRegisterInfo.td               \
-       SIRegisterGetHWRegNum.inc               \
-       AMDILGenRegisterInfo.inc        \
-       AMDILGenInstrInfo.inc           \
-       AMDILGenAsmWriter.inc           \
-       AMDILGenDAGISel.inc             \
-       AMDILGenCallingConv.inc         \
-       AMDILGenSubtargetInfo.inc               \
-       AMDILGenEDInfo.inc              \
-       AMDILGenIntrinsics.inc          \
-       AMDILGenCodeEmitter.inc \
-       AMDGPUInstrEnums.h.include      \
-       AMDGPUInstrEnums.include
-
-CPP_SOURCES := \
-       AMDIL7XXDevice.cpp              \
-       AMDILCFGStructurizer.cpp        \
-       AMDILDevice.cpp                 \
-       AMDILDeviceInfo.cpp             \
-       AMDILEvergreenDevice.cpp        \
-       AMDILFrameLowering.cpp          \
-       AMDILInstrInfo.cpp              \
-       AMDILIntrinsicInfo.cpp          \
-       AMDILISelDAGToDAG.cpp           \
-       AMDILISelLowering.cpp           \
-       AMDILMachinePeephole.cpp        \
-       AMDILMCCodeEmitter.cpp          \
-       AMDILNIDevice.cpp               \
-       AMDILPeepholeOptimizer.cpp      \
-       AMDILRegisterInfo.cpp           \
-       AMDILSIDevice.cpp               \
-       AMDILSubtarget.cpp              \
-       AMDILTargetMachine.cpp          \
-       AMDGPUTargetMachine.cpp         \
-       AMDGPUISelLowering.cpp          \
-       AMDGPUConvertToISA.cpp          \
-       AMDGPULowerInstructions.cpp             \
-       AMDGPUInstrInfo.cpp             \
-       AMDGPURegisterInfo.cpp          \
-       AMDGPUUtil.cpp                  \
-       R600CodeEmitter.cpp             \
-       R600ISelLowering.cpp            \
-       R600InstrInfo.cpp               \
-       R600KernelParameters.cpp        \
-       R600LowerInstructions.cpp       \
-       R600MachineFunctionInfo.cpp     \
-       R600RegisterInfo.cpp            \
-       SIAssignInterpRegs.cpp          \
-       SICodeEmitter.cpp               \
-       SIInstrInfo.cpp                 \
-       SIISelLowering.cpp              \
-       SIMachineFunctionInfo.cpp       \
-       SIPropagateImmReads.cpp         \
-       SIRegisterInfo.cpp              \
-       MCTargetDesc/AMDILMCAsmInfo.cpp \
-       MCTargetDesc/AMDILMCTargetDesc.cpp      \
-       TargetInfo/AMDILTargetInfo.cpp  \
+LLVM_CPP_FILES := \
        radeon_llvm_emit.cpp
 
-C_SOURCES := \
-       radeon_setup_tgsi_llvm.c
+LLVM_C_FILES := \
+       radeon_setup_tgsi_llvm.c \
+       radeon_llvm_util.c