-
-GENERATED_SOURCES := \
- R600Intrinsics.td \
- R600RegisterInfo.td \
- SIRegisterInfo.td \
- SIRegisterGetHWRegNum.inc \
- AMDILGenRegisterInfo.inc \
- AMDILGenInstrInfo.inc \
- AMDILGenAsmWriter.inc \
- AMDILGenDAGISel.inc \
- AMDILGenCallingConv.inc \
- AMDILGenSubtargetInfo.inc \
- AMDILGenEDInfo.inc \
- AMDILGenIntrinsics.inc \
- AMDILGenCodeEmitter.inc
-
-CPP_SOURCES := \
- AMDIL7XXDevice.cpp \
- AMDILCFGStructurizer.cpp \
- AMDILDevice.cpp \
- AMDILDeviceInfo.cpp \
- AMDILEvergreenDevice.cpp \
- AMDILFrameLowering.cpp \
- AMDILInstrInfo.cpp \
- AMDILIntrinsicInfo.cpp \
- AMDILISelDAGToDAG.cpp \
- AMDILISelLowering.cpp \
- AMDILNIDevice.cpp \
- AMDILPeepholeOptimizer.cpp \
- AMDILRegisterInfo.cpp \
- AMDILSIDevice.cpp \
- AMDILSubtarget.cpp \
- AMDGPUTargetMachine.cpp \
- AMDGPUISelLowering.cpp \
- AMDGPUConvertToISA.cpp \
- AMDGPULowerInstructions.cpp \
- AMDGPUInstrInfo.cpp \
- AMDGPURegisterInfo.cpp \
- AMDGPUUtil.cpp \
- R600CodeEmitter.cpp \
- R600ISelLowering.cpp \
- R600InstrInfo.cpp \
- R600KernelParameters.cpp \
- R600LowerInstructions.cpp \
- R600MachineFunctionInfo.cpp \
- R600RegisterInfo.cpp \
- SIAssignInterpRegs.cpp \
- SICodeEmitter.cpp \
- SIInstrInfo.cpp \
- SIISelLowering.cpp \
- SIMachineFunctionInfo.cpp \
- SIPropagateImmReads.cpp \
- SIRegisterInfo.cpp \
- MCTargetDesc/AMDILMCAsmInfo.cpp \
- MCTargetDesc/AMDILMCTargetDesc.cpp \
- TargetInfo/AMDILTargetInfo.cpp \
- radeon_llvm_emit.cpp
-
C_SOURCES := \
- radeon_setup_tgsi_llvm.c
+ cayman_msaa.c \
+ r600_buffer_common.c \
+ r600_cs.h \
+ r600_gpu_load.c \
+ r600_perfcounter.c \
+ r600_pipe_common.c \
+ r600_pipe_common.h \
+ r600_query.c \
+ r600_query.h \
+ r600_streamout.c \
+ r600_test_dma.c \
+ r600_texture.c \
+ r600_viewport.c \
+ radeon_uvd.c \
+ radeon_uvd.h \
+ radeon_vcn_dec.c \
+ radeon_vcn_dec.h \
+ radeon_vce_40_2_2.c \
+ radeon_vce_50.c \
+ radeon_vce_52.c \
+ radeon_vce.c \
+ radeon_vce.h \
+ radeon_video.c \
+ radeon_video.h \
+ radeon_winsys.h