radeon/llvm: Rename all AMDIL* classes to AMDGPU*

[mesa.git] / src / gallium / drivers / radeon / R600InstrInfo.cpp

diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp
index af106b225f94019ca40505f48b3343b91f0fc066..c09e61eb578d0e9953bc027d548e44229bd55d94 100644 (file)
--- a/src/gallium/drivers/radeon/R600InstrInfo.cpp
+++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp
@@ -13,7 +13,12 @@
 
 #include "R600InstrInfo.h"
 #include "AMDGPUTargetMachine.h"
+#include "AMDGPUSubtarget.h"
 #include "R600RegisterInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+
+#define GET_INSTRINFO_CTOR
+#include "AMDGPUGenDFAPacketizer.inc"
 
 using namespace llvm;
 
@@ -33,6 +38,11 @@ bool R600InstrInfo::isTrig(const MachineInstr &MI) const
   return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
 }
 
+bool R600InstrInfo::isVector(const MachineInstr &MI) const
+{
+  return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
+}
+
 void
 R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI, DebugLoc DL,
@@ -40,12 +50,13 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                            bool KillSrc) const
 {
 
-  unsigned subRegMap[4] = {AMDIL::sel_x, AMDIL::sel_y, AMDIL::sel_z, AMDIL::sel_w};
+  unsigned subRegMap[4] = {AMDGPU::sel_x, AMDGPU::sel_y,
+                           AMDGPU::sel_z, AMDGPU::sel_w};
 
-  if (AMDIL::R600_Reg128RegClass.contains(DestReg)
-      && AMDIL::R600_Reg128RegClass.contains(SrcReg)) {
+  if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
+      && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
     for (unsigned i = 0; i < 4; i++) {
-      BuildMI(MBB, MI, DL, get(AMDIL::MOV))
+      BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
               .addReg(RI.getSubReg(DestReg, subRegMap[i]), RegState::Define)
               .addReg(RI.getSubReg(SrcReg, subRegMap[i]))
               .addReg(DestReg, RegState::Define | RegState::Implicit);
@@ -53,87 +64,44 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   } else {
 
     /* We can't copy vec4 registers */
-    assert(!AMDIL::R600_Reg128RegClass.contains(DestReg)
-           && !AMDIL::R600_Reg128RegClass.contains(SrcReg));
+    assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
+           && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
 
-    BuildMI(MBB, MI, DL, get(AMDIL::MOV), DestReg)
+    BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg)
       .addReg(SrcReg, getKillRegState(KillSrc));
   }
 }
 
-unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const
-{
-  switch (opcode) {
-    default: return AMDGPUInstrInfo::getISAOpcode(opcode);
-    case AMDIL::CUSTOM_ADD_i32:
-      return AMDIL::ADD_INT;
-    case AMDIL::CUSTOM_XOR_i32:
-      return AMDIL::XOR_INT;
-    case AMDIL::IEQ:
-      return AMDIL::SETE_INT;
-    case AMDIL::INE:
-      return AMDIL::SETNE_INT;
-    case AMDIL::MOVE_f32:
-    case AMDIL::MOVE_i32:
-      return AMDIL::MOV;
-    case AMDIL::SHR_i32:
-      return getASHRop();
-    case AMDIL::USHR_i32:
-      return getLSHRop();
-  }
-}
-
-unsigned R600InstrInfo::getASHRop() const
+MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
+                                             unsigned DstReg, int64_t Imm) const
 {
-       unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
-       if (gen < AMDILDeviceInfo::HD5XXX) {
-               return AMDIL::ASHR_r600;
-       } else {
-               return AMDIL::ASHR_eg;
-       }
-}
+  MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
+  MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
+  MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X);
+  MachineInstrBuilder(MI).addImm(Imm);
 
-unsigned R600InstrInfo::getLSHRop() const
-{
-  unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
-  if (gen < AMDILDeviceInfo::HD5XXX) {
-    return AMDIL::LSHR_r600;
-  } else {
-    return AMDIL::LSHR_eg;
-  }
+  return MI;
 }
 
-unsigned R600InstrInfo::getMULHI_UINT() const
+unsigned R600InstrInfo::getIEQOpcode() const
 {
-  unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
-
-  if (gen < AMDILDeviceInfo::HD5XXX) {
-    return AMDIL::MULHI_UINT_r600;
-  } else {
-    return AMDIL::MULHI_UINT_eg;
-  }
+  return AMDGPU::SETE_INT;
 }
 
-unsigned R600InstrInfo::getMULLO_UINT() const
+bool R600InstrInfo::isMov(unsigned Opcode) const
 {
-  unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
-
-  if (gen < AMDILDeviceInfo::HD5XXX) {
-    return AMDIL::MULLO_UINT_r600;
-  } else {
-    return AMDIL::MULLO_UINT_eg;
+  switch(Opcode) {
+  default: return false;
+  case AMDGPU::MOV:
+  case AMDGPU::MOV_IMM_F32:
+  case AMDGPU::MOV_IMM_I32:
+    return true;
   }
 }
 
-unsigned R600InstrInfo::getRECIP_UINT() const
+DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
+    const ScheduleDAG *DAG) const
 {
-  const AMDILDevice * dev = TM.getSubtarget<AMDILSubtarget>().device();
-
-  if (dev->getGeneration() < AMDILDeviceInfo::HD5XXX) {
-    return AMDIL::RECIP_UINT_r600;
-  } else if (dev->getDeviceFlag() != OCL_DEVICE_CAYMAN) {
-    return AMDIL::RECIP_UINT_eg;
-  } else {
-    return AMDIL::RECIP_UINT_cm;
-  }
+  const InstrItineraryData *II = TM->getInstrItineraryData();
+  return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
 }