-//===-- R600InstrInfo.cpp - TODO: Add brief description -------===//
+//===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// TODO: Add full description
+// R600 Implementation of TargetInstrInfo.
//
//===----------------------------------------------------------------------===//
#include "R600InstrInfo.h"
#include "AMDGPUTargetMachine.h"
+#include "AMDGPUSubtarget.h"
#include "R600RegisterInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+
+#define GET_INSTRINFO_CTOR
+#include "AMDGPUGenDFAPacketizer.inc"
using namespace llvm;
return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
}
+bool R600InstrInfo::isVector(const MachineInstr &MI) const
+{
+ return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
+}
+
void
R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const
{
- if (!TargetRegisterInfo::isVirtualRegister(SrcReg)
- && AMDIL::GPRI32RegClass.contains(SrcReg)) {
- SrcReg = AMDIL::T0_X;
- }
- BuildMI(MBB, MI, DL, get(AMDIL::MOV), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
-}
-unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const
-{
- switch (opcode) {
- default: return AMDGPUInstrInfo::getISAOpcode(opcode);
- case AMDIL::CUSTOM_ADD_i32:
- return AMDIL::ADD_INT;
- case AMDIL::CUSTOM_XOR_i32:
- return AMDIL::XOR_INT;
- case AMDIL::MOVE_f32:
- case AMDIL::MOVE_i32:
- return AMDIL::MOV;
- case AMDIL::SHR_i32:
- return getLSHRop();
- }
-}
+ unsigned subRegMap[4] = {AMDGPU::sel_x, AMDGPU::sel_y,
+ AMDGPU::sel_z, AMDGPU::sel_w};
-unsigned R600InstrInfo::getLSHRop() const
-{
- unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
- if (gen < AMDILDeviceInfo::HD5XXX) {
- return AMDIL::LSHR_r600;
+ if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
+ && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
+ for (unsigned i = 0; i < 4; i++) {
+ BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
+ .addReg(RI.getSubReg(DestReg, subRegMap[i]), RegState::Define)
+ .addReg(RI.getSubReg(SrcReg, subRegMap[i]))
+ .addReg(DestReg, RegState::Define | RegState::Implicit);
+ }
} else {
- return AMDIL::LSHR_eg;
+
+ /* We can't copy vec4 registers */
+ assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
+ && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
+
+ BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
}
}
-unsigned R600InstrInfo::getMULHI_UINT() const
+MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
+ unsigned DstReg, int64_t Imm) const
{
- unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
+ MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
+ MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
+ MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X);
+ MachineInstrBuilder(MI).addImm(Imm);
- if (gen < AMDILDeviceInfo::HD5XXX) {
- return AMDIL::MULHI_UINT_r600;
- } else {
- return AMDIL::MULHI_UINT_eg;
- }
+ return MI;
}
-unsigned R600InstrInfo::getMULLO_UINT() const
+unsigned R600InstrInfo::getIEQOpcode() const
{
- unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
+ return AMDGPU::SETE_INT;
+}
- if (gen < AMDILDeviceInfo::HD5XXX) {
- return AMDIL::MULLO_UINT_r600;
- } else {
- return AMDIL::MULLO_UINT_eg;
+bool R600InstrInfo::isMov(unsigned Opcode) const
+{
+ switch(Opcode) {
+ default: return false;
+ case AMDGPU::MOV:
+ case AMDGPU::MOV_IMM_F32:
+ case AMDGPU::MOV_IMM_I32:
+ return true;
}
}
-unsigned R600InstrInfo::getRECIP_UINT() const
+DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM,
+ const ScheduleDAG *DAG) const
{
- const AMDILDevice * dev = TM.getSubtarget<AMDILSubtarget>().device();
-
- if (dev->getGeneration() < AMDILDeviceInfo::HD5XXX) {
- return AMDIL::RECIP_UINT_r600;
- } else if (dev->getDeviceFlag() != OCL_DEVICE_CAYMAN) {
- return AMDIL::RECIP_UINT_eg;
- } else {
- return AMDIL::RECIP_UINT_cm;
- }
+ const InstrItineraryData *II = TM->getInstrItineraryData();
+ return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
}