radeon/llvm: Move lowering of SETCC node to R600ISelLowering

[mesa.git] / src / gallium / drivers / radeon / R600InstrInfo.h

diff --git a/src/gallium/drivers/radeon/R600InstrInfo.h b/src/gallium/drivers/radeon/R600InstrInfo.h
index 014eeb0b9f7e89764d7786fab38d5d02d884ab93..b9cbcc81a5e9e96aa24d6b1b3bfc387424f55792 100644 (file)
--- a/src/gallium/drivers/radeon/R600InstrInfo.h
+++ b/src/gallium/drivers/radeon/R600InstrInfo.h
@@ -22,14 +22,9 @@
 
 namespace llvm {
 
-  struct InstrGroup {
-    unsigned amdil;
-    unsigned r600;
-    unsigned eg;
-    unsigned cayman;
-  };
-
   class AMDGPUTargetMachine;
+  class DFAPacketizer;
+  class ScheduleDAG;
   class MachineFunction;
   class MachineInstr;
   class MachineInstrBuilder;
@@ -48,16 +43,21 @@ namespace llvm {
                            unsigned DestReg, unsigned SrcReg,
                            bool KillSrc) const;
 
-  virtual unsigned getISAOpcode(unsigned opcode) const;
   bool isTrig(const MachineInstr &MI) const;
 
-  unsigned getLSHRop() const;
-  unsigned getASHRop() const;
-  unsigned getMULHI_UINT() const;
-  unsigned getMULLO_UINT() const;
-  unsigned getRECIP_UINT() const;
+  /// isVector - Vector instructions are instructions that must fill all
+  /// instruction slots within an instruction group.
+  bool isVector(const MachineInstr &MI) const;
+
+  virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
+                                        int64_t Imm) const;
+
+  virtual unsigned getIEQOpcode() const;
+  virtual bool isMov(unsigned Opcode) const;
 
-  };
+  DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
+                                           const ScheduleDAG *DAG) const;
+};
 
 } // End llvm namespace
 
@@ -68,7 +68,8 @@ namespace R600_InstFlag {
                REDUCTION = (1 << 2),
                FC = (1 << 3),
                TRIG = (1 << 4),
-               OP3 = (1 << 5)
+               OP3 = (1 << 5),
+               VECTOR = (1 << 6)
        };
 }