radeon/llvm: improve cube map handling

[mesa.git] / src / gallium / drivers / radeon / R600Instructions.td

diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td
index feb97fac82263790043c4135a8f0f2e953b991db..120a71c5b9ef687018420099776a5712aa4b1da1 100644 (file)
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -399,7 +399,7 @@ def RNDNE : R600_1OP <
 
 def FLOOR : R600_1OP <
   0x14, "FLOOR",
-  [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
+  [(set R600_Reg32:$dst, (ffloor R600_Reg32:$src))]
 >;
 
 def MOV : InstR600 <0x19, (outs R600_Reg32:$dst),
@@ -545,7 +545,25 @@ def SETGE_UINT : R600_2OP <
 def CNDE_INT : R600_3OP <
        0x1C, "CNDE_INT",
   [(set (i32 R600_Reg32:$dst),
-   (select R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
+   (selectcc (i32 R600_Reg32:$src0), 0,
+       (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
+       COND_EQ))]
+>;
+
+def CNDGE_INT : R600_3OP <
+       0x1E, "CNDGE_INT",
+  [(set (i32 R600_Reg32:$dst),
+   (selectcc (i32 R600_Reg32:$src0), 0,
+       (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
+       COND_GE))]
+>;
+
+def CNDGT_INT : R600_3OP <
+       0x1D, "CNDGT_INT",
+  [(set (i32 R600_Reg32:$dst),
+   (selectcc (i32 R600_Reg32:$src0), 0,
+       (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2),
+       COND_GT))]
 >;
 
 //===----------------------------------------------------------------------===//
@@ -642,18 +660,26 @@ class MULADD_Common <bits<11> inst> : R600_3OP <
 
 class CNDE_Common <bits<11> inst> : R600_3OP <
   inst, "CNDE",
-  [(set (f32 R600_Reg32:$dst),
-   (select (i32 (fp_to_sint (fneg R600_Reg32:$src0))), (f32 R600_Reg32:$src2), (f32 R600_Reg32:$src1)))]
+  [(set R600_Reg32:$dst,
+   (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
+       (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
+       COND_EQ))]
 >;
 
 class CNDGT_Common <bits<11> inst> : R600_3OP <
   inst, "CNDGT",
-  []
+  [(set R600_Reg32:$dst,
+   (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
+       (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
+       COND_GT))]
 >;
-  
+
 class CNDGE_Common <bits<11> inst> : R600_3OP <
   inst, "CNDGE",
-  [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
+  [(set R600_Reg32:$dst,
+   (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
+       (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2),
+       COND_GE))]
 >;
 
 class DOT4_Common <bits<11> inst> : R600_REDUCTION <
@@ -735,7 +761,7 @@ class LOG_CLAMPED_Common <bits<11> inst> : R600_1OP <
 
 class LOG_IEEE_Common <bits<11> inst> : R600_1OP <
   inst, "LOG_IEEE",
-  [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))]
+  [(set R600_Reg32:$dst, (flog2 R600_Reg32:$src))]
 >;
 
 class LSHL_Common <bits<11> inst> : R600_2OP <
@@ -879,8 +905,13 @@ let Predicates = [isR600] in {
 
 // Helper pattern for normalizing inputs to triginomic instructions for R700+
 // cards.
-class TRIG_eg <InstR600 trig, Intrinsic intr> : Pat<
-  (intr R600_Reg32:$src),
+class COS_PAT <InstR600 trig> : Pat<
+  (fcos R600_Reg32:$src),
+  (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
+>;
+
+class SIN_PAT <InstR600 trig> : Pat<
+  (fsin R600_Reg32:$src),
   (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), R600_Reg32:$src))
 >;
 
@@ -893,8 +924,8 @@ let Predicates = [isR700] in {
   def COS_r700 : COS_Common<0x6F>;
 
   // R700 normalizes inputs to SIN/COS the same as EG
-  def : TRIG_eg <SIN_r700, int_AMDGPU_sin>;
-  def : TRIG_eg <COS_r700, int_AMDGPU_cos>;
+  def : SIN_PAT <SIN_r700>;
+  def : COS_PAT <COS_r700>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -971,8 +1002,8 @@ let Predicates = [isEGorCayman] in {
   def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
   def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
 
-  def : TRIG_eg <SIN_eg, int_AMDGPU_sin>;
-  def : TRIG_eg <COS_eg, int_AMDGPU_cos>;
+  def : SIN_PAT <SIN_eg>;
+  def : COS_PAT <COS_eg>;
 
   def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
     let Pattern = [];
@@ -992,6 +1023,9 @@ let Predicates = [isEGorCayman] in {
   def : Pat<(fp_to_uint R600_Reg32:$src),
     (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>;
 
+  def : Pat<(fsqrt R600_Reg32:$src),
+    (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_eg R600_Reg32:$src))>;
+
 //===----------------------------------------------------------------------===//
 // Memory read/write instructions
 //===----------------------------------------------------------------------===//