radeon/llvm: Move lowering of SETCC node to R600ISelLowering

[mesa.git] / src / gallium / drivers / radeon / SIGenRegisterInfo.pl

diff --git a/src/gallium/drivers/radeon/SIGenRegisterInfo.pl b/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
index 644daa1bc220e403abc103d2aec604c0fd5bbbc2..68b4fe357faa930841e3525304ebf9ebad105eeb 100644 (file)
--- a/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
+++ b/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
@@ -1,16 +1,17 @@
-#===-- SIGenRegisterInfo.pl - TODO: Add brief description -------===#
+#===-- SIGenRegisterInfo.pl - Script for generating register info files ----===#
 #
 #                     The LLVM Compiler Infrastructure
 #
 # This file is distributed under the University of Illinois Open Source
 # License. See LICENSE.TXT for details.
 #
-#===----------------------------------------------------------------------===#
+#===------------------------------------------------------------------------===#
 #
-# TODO: Add full description
+# This perl script prints to stdout .td code to be used as SIRegisterInfo.td
+# it also generates a file called SIHwRegInfo.include, which contains helper
+# functions for determining the hw encoding of registers.
 #
-#===----------------------------------------------------------------------===#
-
+#===------------------------------------------------------------------------===#
 
 use strict;
 use warnings;
@@ -25,7 +26,7 @@ my $INDEX_FILE = defined($ARGV[0]) ? $ARGV[0] : '';
 
 print <<STRING;
 
-let Namespace = "AMDIL" in {
+let Namespace = "AMDGPU" in {
   def low : SubRegIndex;
   def high : SubRegIndex;
 
@@ -40,21 +41,21 @@ let Namespace = "AMDIL" in {
 }
 
 class SIReg <string n> : Register<n> {
-  let Namespace = "AMDIL";
+  let Namespace = "AMDGPU";
 }
 
 class SI_64 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
-  let Namespace = "AMDIL";
+  let Namespace = "AMDGPU";
   let SubRegIndices = [low, high];
 }
 
 class SI_128 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
-  let Namespace = "AMDIL";
+  let Namespace = "AMDGPU";
   let SubRegIndices = [sel_x, sel_y, sel_z, sel_w];
 }
 
 class SI_256 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
-  let Namespace = "AMDIL";
+  let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
 }
 
@@ -65,11 +66,10 @@ class SGPR_32 <bits<8> num, string name> : SIReg<name> {
 }
 
 
-class VGPR_32 <bits<9> num, string name, Register gprf32_alias> : SIReg<name> {
+class VGPR_32 <bits<9> num, string name> : SIReg<name> {
   field bits<9> Num;
 
   let Num = num;
-  let Aliases = [gprf32_alias];
 }
 
 class SGPR_64 <bits<8> num, string name, list<Register> subregs> :
@@ -131,22 +131,18 @@ for (my $i = 0; $i < $SGPR_COUNT; $i++) {
 }
 
 my @VGPR;
-my @GPRF32;
 for (my $i = 0; $i < $VGPR_COUNT; $i++) {
-  my $gprf32_num = $i + 1;
-  my $gprf32_name = "R$gprf32_num";
-  print "def VGPR$i : VGPR_32 <$i, \"VGPR$i\", $gprf32_name>;\n";
+  print "def VGPR$i : VGPR_32 <$i, \"VGPR$i\">;\n";
   $VGPR[$i] = "VGPR$i";
-  $GPRF32[$i] = $gprf32_name;
 }
 
 print <<STRING;
 
-def SReg_32 : RegisterClass<"AMDIL", [f32, i32], 32,
+def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
     (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX),  SREG_LIT_0, M0)
 >;
 
-def VReg_32 : RegisterClass<"AMDIL", [f32, i32], 32,
+def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
     (add (sequence "VGPR%u", 0, $VGPR_MAX_IDX),
     PERSP_SAMPLE_I, PERSP_SAMPLE_J,
     PERSP_CENTER_I, PERSP_CENTER_J,
@@ -167,13 +163,11 @@ def VReg_32 : RegisterClass<"AMDIL", [f32, i32], 32,
     )
 >;
 
-def AllReg_32 : RegisterClass<"AMDIL", [f32, i32], 32,
-    (add VReg_32,
-         SReg_32,
-         (sequence "R%u", 1, $VGPR_COUNT))
+def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
+    (add VReg_32, SReg_32)
 >;
 
-def CCReg : RegisterClass<"AMDIL", [f32], 32, (add VCC, SCC)>;
+def CCReg : RegisterClass<"AMDGPU", [f32], 32, (add VCC, SCC)>;
 
 STRING
 
@@ -181,8 +175,8 @@ my @subregs_64 = ('low', 'high');
 my @subregs_128 = ('sel_x', 'sel_y', 'sel_z', 'sel_w');
 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
 
-my @SGPR64 = print_sgpr_class(64, \@subregs_64, ('i64', 'iPTRAny'));
-my @SGPR128 = print_sgpr_class(128, \@subregs_128, ('v4f32'));
+my @SGPR64 = print_sgpr_class(64, \@subregs_64, ('i64'));
+my @SGPR128 = print_sgpr_class(128, \@subregs_128, ('v4f32', 'v4i32'));
 my @SGPR256 = print_sgpr_class(256, \@subregs_256, ('v8i32'));
 
 my @VGPR64 = print_vgpr_class(64, \@subregs_64, ('i64'));
@@ -193,7 +187,7 @@ my $sgpr64_list = join(',', @SGPR64);
 my $vgpr64_list = join(',', @VGPR64);
 print <<STRING;
 
-def AllReg_64 : RegisterClass<"AMDIL", [f64, i64], 64,
+def AllReg_64 : RegisterClass<"AMDGPU", [f64, i64], 64,
     (add $sgpr64_list, $vgpr64_list)
 >;
 
@@ -235,7 +229,7 @@ if ($INDEX_FILE ne '') {
   for my $key (keys(%hw_values)) {
     my @names = @{$hw_values{$key}};
     for my $regname (@names) {
-      print $fh "  case AMDIL::$regname:\n"
+      print $fh "  case AMDGPU::$regname:\n"
     }
     print $fh "    return $key;\n";
   }
@@ -272,7 +266,7 @@ sub print_reg_class {
   }
   my $reg_list = join(', ', @registers);
 
-  print "def $class_prefix\_$reg_width : RegisterClass<\"AMDIL\", [" . join (', ', @types) . "], $reg_width,\n  (add $reg_list)\n>{\n";
+  print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n  (add $reg_list)\n>{\n";
   print "  let SubRegClasses = [($class_prefix\_", ($reg_width / $component_count) , ' ', join(', ', @{$sub_reg_ref}), ")];\n}\n";
   return @registers;
 }