radeon/llvm: Move lowering of SETCC node to R600ISelLowering

[mesa.git] / src / gallium / drivers / radeon / SIInstrInfo.cpp

diff --git a/src/gallium/drivers/radeon/SIInstrInfo.cpp b/src/gallium/drivers/radeon/SIInstrInfo.cpp
index 058c772e620a80d9a48f7a49c04d274a18241feb..4438d67f877644fbfef8aa353c5ba69507a56bd1 100644 (file)
--- a/src/gallium/drivers/radeon/SIInstrInfo.cpp
+++ b/src/gallium/drivers/radeon/SIInstrInfo.cpp
@@ -38,7 +38,7 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                            unsigned DestReg, unsigned SrcReg,
                            bool KillSrc) const
 {
-  BuildMI(MBB, MI, DL, get(AMDIL::V_MOV_B32_e32), DestReg)
+  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
    .addReg(SrcReg, getKillRegState(KillSrc));
 }
 
@@ -59,7 +59,7 @@ unsigned SIInstrInfo::getEncodingBytes(const MachineInstr &MI) const
   }
 
   /* This instruction always has a literal */
-  if (MI.getOpcode() == AMDIL::S_MOV_IMM_I32) {
+  if (MI.getOpcode() == AMDGPU::S_MOV_IMM_I32) {
     return 8;
   }
 
@@ -77,38 +77,10 @@ unsigned SIInstrInfo::getEncodingBytes(const MachineInstr &MI) const
   }
 }
 
-MachineInstr * SIInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
-    DebugLoc DL) const
-{
-  MachineInstr * newMI = AMDGPUInstrInfo::convertToISA(MI, MF, DL);
-  const MCInstrDesc &newDesc = get(newMI->getOpcode());
-
-  /* If this instruction was converted to a VOP3, we need to add the extra
-   * operands for abs, clamp, omod, and negate. */
-  if (getEncodingType(*newMI) == SIInstrEncodingType::VOP3
-      && newMI->getNumOperands() < newDesc.getNumOperands()) {
-    MachineInstrBuilder builder(newMI);
-    for (unsigned op_idx = newMI->getNumOperands();
-                  op_idx < newDesc.getNumOperands(); op_idx++) {
-      builder.addImm(0);
-    }
-  }
-  return newMI;
-}
-
-unsigned SIInstrInfo::getISAOpcode(unsigned AMDILopcode) const
-{
-  switch (AMDILopcode) {
-  //XXX We need a better way of detecting end of program
-  case AMDIL::MOVE_f32: return AMDIL::V_MOV_B32_e32;
-  default: return AMDILopcode;
-  }
-}
-
 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
                                            int64_t Imm) const
 {
-  MachineInstr * MI = MF->CreateMachineInstr(get(AMDIL::V_MOV_IMM_I32), DebugLoc());
+  MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
   MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
   MachineInstrBuilder(MI).addImm(Imm);
 
@@ -120,13 +92,13 @@ bool SIInstrInfo::isMov(unsigned Opcode) const
 {
   switch(Opcode) {
   default: return false;
-  case AMDIL::S_MOV_B32:
-  case AMDIL::S_MOV_B64:
-  case AMDIL::V_MOV_B32_e32:
-  case AMDIL::V_MOV_B32_e64:
-  case AMDIL::V_MOV_IMM_F32:
-  case AMDIL::V_MOV_IMM_I32:
-  case AMDIL::S_MOV_IMM_I32:
+  case AMDGPU::S_MOV_B32:
+  case AMDGPU::S_MOV_B64:
+  case AMDGPU::V_MOV_B32_e32:
+  case AMDGPU::V_MOV_B32_e64:
+  case AMDGPU::V_MOV_IMM_F32:
+  case AMDGPU::V_MOV_IMM_I32:
+  case AMDGPU::S_MOV_IMM_I32:
     return true;
   }
 }