radeon/llvm: Move lowering of SETCC node to R600ISelLowering

[mesa.git] / src / gallium / drivers / radeon / SIInstrInfo.cpp

diff --git a/src/gallium/drivers/radeon/SIInstrInfo.cpp b/src/gallium/drivers/radeon/SIInstrInfo.cpp
index 6f92e96c6e785642a749b293292a87b5d1ecd04c..4438d67f877644fbfef8aa353c5ba69507a56bd1 100644 (file)
--- a/src/gallium/drivers/radeon/SIInstrInfo.cpp
+++ b/src/gallium/drivers/radeon/SIInstrInfo.cpp
@@ -1,4 +1,4 @@
-//===-- SIInstrInfo.cpp - TODO: Add brief description -------===//
+//===-- SIInstrInfo.cpp - SI Instruction Information  ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// TODO: Add full description
+// SI Implementation of TargetInstrInfo.
 //
 //===----------------------------------------------------------------------===//
 
@@ -38,7 +38,7 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                            unsigned DestReg, unsigned SrcReg,
                            bool KillSrc) const
 {
-  BuildMI(MBB, MI, DL, get(AMDIL::V_MOV_B32_e32), DestReg)
+  BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
    .addReg(SrcReg, getKillRegState(KillSrc));
 }
 
@@ -59,7 +59,7 @@ unsigned SIInstrInfo::getEncodingBytes(const MachineInstr &MI) const
   }
 
   /* This instruction always has a literal */
-  if (MI.getOpcode() == AMDIL::S_MOV_IMM_I32) {
+  if (MI.getOpcode() == AMDGPU::S_MOV_IMM_I32) {
     return 8;
   }
 
@@ -77,97 +77,28 @@ unsigned SIInstrInfo::getEncodingBytes(const MachineInstr &MI) const
   }
 }
 
-MachineInstr * SIInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
-    DebugLoc DL) const
+MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
+                                           int64_t Imm) const
 {
+  MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
+  MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
+  MachineInstrBuilder(MI).addImm(Imm);
 
-  switch (MI.getOpcode()) {
-    default: break;
-    case AMDIL::ABS_f32: return convertABS_f32(MI, MF, DL);
-    case AMDIL::CLAMP_f32: return convertCLAMP_f32(MI, MF, DL);
-  }
-
-  MachineInstr * newMI = AMDGPUInstrInfo::convertToISA(MI, MF, DL);
-  const MCInstrDesc &newDesc = get(newMI->getOpcode());
-
-  /* If this instruction was converted to a VOP3, we need to add the extra
-   * operands for abs, clamp, omod, and negate. */
-  if (getEncodingType(*newMI) == SIInstrEncodingType::VOP3
-      && newMI->getNumOperands() < newDesc.getNumOperands()) {
-    MachineInstrBuilder builder(newMI);
-    for (unsigned op_idx = newMI->getNumOperands();
-                  op_idx < newDesc.getNumOperands(); op_idx++) {
-      builder.addImm(0);
-    }
-  }
-  return newMI;
-}
-
-unsigned SIInstrInfo::getISAOpcode(unsigned AMDILopcode) const
-{
-  switch (AMDILopcode) {
-  case AMDIL::MAD_f32: return AMDIL::V_MAD_LEGACY_F32;
-  default: return AMDGPUInstrInfo::getISAOpcode(AMDILopcode);
-  }
-}
-
-MachineInstr * SIInstrInfo::convertABS_f32(MachineInstr & absInstr,
-    MachineFunction &MF, DebugLoc DL) const
-{
-  MachineRegisterInfo &MRI = MF.getRegInfo();
-  MachineOperand &dst = absInstr.getOperand(0);
-
-  /* Convert the desination register to the VReg_32 class */
-  if (TargetRegisterInfo::isVirtualRegister(dst.getReg())) {
-    MRI.setRegClass(dst.getReg(), AMDIL::VReg_32RegisterClass);
-  }
+  return MI;
 
-  return BuildMI(MF, DL, get(AMDIL::V_MOV_B32_e64))
-                 .addOperand(absInstr.getOperand(0))
-                 .addOperand(absInstr.getOperand(1))
-                /* VSRC1-2 are unused, but we still need to fill all the
-                 * operand slots, so we just reuse the VSRC0 operand */
-                 .addOperand(absInstr.getOperand(1))
-                 .addOperand(absInstr.getOperand(1))
-                 .addImm(1) // ABS
-                 .addImm(0) // CLAMP
-                 .addImm(0) // OMOD
-                 .addImm(0); // NEG
 }
 
-MachineInstr * SIInstrInfo::convertCLAMP_f32(MachineInstr & clampInstr,
-    MachineFunction &MF, DebugLoc DL) const
+bool SIInstrInfo::isMov(unsigned Opcode) const
 {
-  MachineRegisterInfo &MRI = MF.getRegInfo();
-  /* XXX: HACK assume that low == zero and high == one for now until
-   * we have a way to propogate the immediates. */
-
-/*
-  uint32_t zero = (uint32_t)APFloat(0.0f).bitcastToAPInt().getZExtValue();
-  uint32_t one = (uint32_t)APFloat(1.0f).bitcastToAPInt().getZExtValue();
-  uint32_t low = clampInstr.getOperand(2).getImm();
-  uint32_t high = clampInstr.getOperand(3).getImm();
-*/
-//  if (low == zero && high == one) {
-  
-  /* Convert the desination register to the VReg_32 class */
-  if (TargetRegisterInfo::isVirtualRegister(clampInstr.getOperand(0).getReg())) {
-    MRI.setRegClass(clampInstr.getOperand(0).getReg(),
-                    AMDIL::VReg_32RegisterClass);
+  switch(Opcode) {
+  default: return false;
+  case AMDGPU::S_MOV_B32:
+  case AMDGPU::S_MOV_B64:
+  case AMDGPU::V_MOV_B32_e32:
+  case AMDGPU::V_MOV_B32_e64:
+  case AMDGPU::V_MOV_IMM_F32:
+  case AMDGPU::V_MOV_IMM_I32:
+  case AMDGPU::S_MOV_IMM_I32:
+    return true;
   }
-  return BuildMI(MF, DL, get(AMDIL::V_MOV_B32_e64))
-           .addOperand(clampInstr.getOperand(0))
-           .addOperand(clampInstr.getOperand(1))
-          /* VSRC1-2 are unused, but we still need to fill all the
-           * operand slots, so we just reuse the VSRC0 operand */
-           .addOperand(clampInstr.getOperand(1))
-           .addOperand(clampInstr.getOperand(1))
-           .addImm(0) // ABS
-           .addImm(1) // CLAMP
-           .addImm(0) // OMOD
-           .addImm(0); // NEG
-//  } else {
-    /* XXX: Handle other cases */
-//    abort();
-//  }
 }