radeon-llvm: Start multithreaded before using llvm.

[mesa.git] / src / gallium / drivers / radeon / SIInstrInfo.td

diff --git a/src/gallium/drivers/radeon/SIInstrInfo.td b/src/gallium/drivers/radeon/SIInstrInfo.td
index 435948ff1decb530245fd05cff84c85b2928ae37..81df55d135efba65f1ee7f94cb660f09fa24649e 100644 (file)
--- a/src/gallium/drivers/radeon/SIInstrInfo.td
+++ b/src/gallium/drivers/radeon/SIInstrInfo.td
@@ -7,7 +7,26 @@
 //
 //===----------------------------------------------------------------------===//
 
+//===----------------------------------------------------------------------===//
+// SI DAG Profiles
+//===----------------------------------------------------------------------===//
+def SDTVCCBinaryOp : SDTypeProfile<1, 2, [
+  SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 2>
+]>;
+
+//===----------------------------------------------------------------------===//
+// SI DAG Nodes
+//===----------------------------------------------------------------------===//
+
+// and operation on 64-bit wide vcc
+def SIvcc_and : SDNode<"SIISD::VCC_AND", SDTVCCBinaryOp,
+  [SDNPCommutative, SDNPAssociative]
+>;
 
+// Special bitcast node for sharing VCC register between VALU and SALU
+def SIvcc_bitcast : SDNode<"SIISD::VCC_BITCAST",
+  SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>
+>;
 
 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
     AMDGPUInst<outs, ins, asm, pattern> {
@@ -32,6 +51,31 @@ class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
   field bits<64> Inst;
 }
 
+class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
+  let EncoderMethod = "encodeOperand";
+  let MIOperandInfo = opInfo;
+}
+
+def IMM16bit : ImmLeaf <
+  i16,
+  [{return isInt<16>(Imm);}]
+>;
+
+def IMM8bit : ImmLeaf <
+  i32,
+  [{return (int32_t)Imm >= 0 && (int32_t)Imm <= 0xff;}]
+>;
+
+def IMM12bit : ImmLeaf <
+  i16,
+  [{return (int16_t)Imm >= 0 && (int16_t)Imm <= 0xfff;}]
+>;
+
+def IMM32bitIn64bit : ImmLeaf <
+  i64,
+  [{return isInt<32>(Imm);}]
+>;
+
 class GPR4Align <RegisterClass rc> : Operand <vAny> {
   let EncoderMethod = "GPR4AlignEncode";
   let MIOperandInfo = (ops rc:$reg); 
@@ -46,6 +90,25 @@ def i32Literal : Operand <i32> {
   let EncoderMethod = "i32LiteralEncode";
 }
 
+// i64Literal uses the same encoder method as i32 literal, because an
+// i64Literal is really a i32 literal with the top 32-bits all set to zero.
+def i64Literal : Operand <i64> {
+  let EncoderMethod = "i32LiteralEncode";
+}
+
+def SMRDmemrr : Operand<iPTR> {
+  let MIOperandInfo = (ops SReg_64, SReg_32);
+  let EncoderMethod = "GPR2AlignEncode";
+}
+
+def SMRDmemri : Operand<iPTR> {
+  let MIOperandInfo = (ops SReg_64, i32imm);
+  let EncoderMethod = "SMRDmemriEncode";
+}
+
+def ADDR_Reg     : ComplexPattern<i64, 2, "SelectADDRReg", [], []>;
+def ADDR_Offset8 : ComplexPattern<i64, 2, "SelectADDR8BitOffset", [], []>;
+
 def EXP : Enc64<
   (outs),
   (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
@@ -196,9 +259,10 @@ class SMRD <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
     Enc32<outs, ins, asm, pattern> {
 
   bits<7> SDST;
-  bits<8> OFFSET;
-  bits<6> SBASE;
-  bits<1> IMM = 0; // Determined by subclasses
+  bits<15> PTR;
+  bits<8> OFFSET = PTR{7-0};
+  bits<1> IMM    = PTR{8};
+  bits<6> SBASE  = PTR{14-9};
   
   let Inst{7-0} = OFFSET;
   let Inst{8} = IMM;
@@ -251,6 +315,8 @@ class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
   let Inst{22-16} = op;
   let Inst{31-23} = 0x17e;
   let EncodingType = 8; // SIInstrEncodingType::SOPC
+
+  let DisableEncoding = "$dst";
 }
 
 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
@@ -266,11 +332,11 @@ class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
   let EncodingType = 9; // SIInstrEncodingType::SOPK
 }
 
-class SOPP <bits<7> op, dag ins, string asm> : Enc32 <
+class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
   (outs),
   ins,
   asm,
-  [] > {
+  pattern > {
 
   bits <16> SIMM16;
 
@@ -359,8 +425,8 @@ class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
   let PostEncoderMethod = "VOPPostEncode";
 }
 
-class VOPC <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
-    Enc32 <outs, ins, asm, pattern> {
+class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
+    Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
 
   bits<9> SRC0;
   bits<8> VSRC1;
@@ -372,8 +438,7 @@ class VOPC <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
  
   let EncodingType = 15; //SIInstrEncodingType::VOPC
   let PostEncoderMethod = "VOPPostEncode";
-
-  let Defs = [VCC];
+  let DisableEncoding = "$dst";
 }
 
 class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
@@ -419,45 +484,29 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU
   let mayStore = 1;
 }
 
-/*XXX: We should be able to infer the imm bit based on the arg types */
-multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
-
-  def _SGPR : SMRD <
+multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass,
+                       ValueType vt> {
+  def _IMM : SMRD <
               op,
               (outs dstClass:$dst),
-              (ins SReg_32:$offset, GPR2Align<SReg_64,i64>:$sbase),
+              (ins SMRDmemri:$src0),
               asm,
-              []
-  > {
-    let IMM = 0;
-  }
+              [(set (vt dstClass:$dst), (constant_load ADDR_Offset8:$src0))]
+  >;
 
-  def _IMM : SMRD <
+  def _SGPR : SMRD <
               op,
               (outs dstClass:$dst),
-              (ins i32imm:$offset, GPR2Align<SReg_64,i64>:$sbase),
+              (ins SMRDmemrr:$src0),
               asm,
-              []
-  > {
-    let IMM = 1;
-  }
+              [(set (vt dstClass:$dst), (constant_load ADDR_Reg:$src0))]
+  >;
 }
 
-class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
-  let EncoderMethod = "encodeOperand";
-  let MIOperandInfo = opInfo;
+multiclass SMRD_32 <bits<5> op, string asm, RegisterClass dstClass> {
+  defm _F32 : SMRD_Helper <op, asm, dstClass, f32>;
+  defm _I32 : SMRD_Helper <op, asm, dstClass, i32>;
 }
 
-def IMM8bit : ImmLeaf <
-  i32,
-  [{return (int32_t)Imm >= 0 && (int32_t)Imm <= 0xff;}]
->;
-
-def IMM12bit : ImmLeaf <
-  i16,
-  [{return (int16_t)Imm >= 0 && (int16_t)Imm <= 0xfff;}]
->;
-
 include "SIInstrFormats.td"
-
 include "SIInstructions.td"