radeon/llvm: Move lowering of SETCC node to R600ISelLowering

[mesa.git] / src / gallium / drivers / radeon / SIRegisterInfo.cpp

diff --git a/src/gallium/drivers/radeon/SIRegisterInfo.cpp b/src/gallium/drivers/radeon/SIRegisterInfo.cpp
index 04e2e17d7ec8fe7e94ff9b49fbda7e6fa3b52e92..0d0e612080e44e178dbd7fb130e00f3ab2f563d4 100644 (file)
--- a/src/gallium/drivers/radeon/SIRegisterInfo.cpp
+++ b/src/gallium/drivers/radeon/SIRegisterInfo.cpp
@@ -34,8 +34,8 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const
 unsigned SIRegisterInfo::getBinaryCode(unsigned reg) const
 {
   switch (reg) {
-    case AMDIL::M0: return 124;
-    case AMDIL::SREG_LIT_0: return 128;
+    case AMDGPU::M0: return 124;
+    case AMDGPU::SREG_LIT_0: return 128;
     default: return getHWRegNum(reg);
   }
 }
@@ -44,13 +44,18 @@ const TargetRegisterClass *
 SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
 {
   switch (rc->getID()) {
-  case AMDIL::GPRF32RegClassID:
-    return &AMDIL::VReg_32RegClass;
-  case AMDIL::GPRV4F32RegClassID:
-  case AMDIL::GPRV4I32RegClassID:
-    return &AMDIL::VReg_128RegClass;
+  case AMDGPU::GPRF32RegClassID:
+    return &AMDGPU::VReg_32RegClass;
   default: return rc;
   }
 }
 
+const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
+                                                                   MVT VT) const
+{
+  switch(VT.SimpleTy) {
+    default:
+    case MVT::i32: return AMDGPU::VReg_32RegisterClass;
+  }
+}
 #include "SIRegisterGetHWRegNum.inc"