radeon/llvm: improve cube map handling

[mesa.git] / src / gallium / drivers / radeon / SIRegisterInfo.h

diff --git a/src/gallium/drivers/radeon/SIRegisterInfo.h b/src/gallium/drivers/radeon/SIRegisterInfo.h
index c797e3c8aceea9be588449ce989cc78c49c9ed5b..99005cbccc174d50f5acfb90faaefd99d18a99fe 100644 (file)
--- a/src/gallium/drivers/radeon/SIRegisterInfo.h
+++ b/src/gallium/drivers/radeon/SIRegisterInfo.h
@@ -1,4 +1,4 @@
-//===-- SIRegisterInfo.h - TODO: Add brief description -------===//
+//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// TODO: Add full description
+// Interface definition for SIRegisterInfo
 //
 //===----------------------------------------------------------------------===//
 
@@ -19,27 +19,35 @@
 
 namespace llvm {
 
-  class AMDGPUTargetMachine;
-  class TargetInstrInfo;
+class AMDGPUTargetMachine;
+class TargetInstrInfo;
 
-  struct SIRegisterInfo : public AMDGPURegisterInfo
-  {
-    AMDGPUTargetMachine &TM;
-    const TargetInstrInfo &TII;
+struct SIRegisterInfo : public AMDGPURegisterInfo
+{
+  AMDGPUTargetMachine &TM;
+  const TargetInstrInfo &TII;
 
-    SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
+  SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
 
-    virtual BitVector getReservedRegs(const MachineFunction &MF) const;
-    virtual unsigned getBinaryCode(unsigned reg) const;
+  virtual BitVector getReservedRegs(const MachineFunction &MF) const;
 
-    virtual bool isBaseRegClass(unsigned regClassID) const;
+  /// getBinaryCode - Returns the hardware encoding for a register
+  virtual unsigned getBinaryCode(unsigned reg) const;
 
-    virtual const TargetRegisterClass *
+  /// getISARegClass - rc is an AMDIL reg class.  This function returns the
+  /// SI register class that is equivalent to the given AMDIL register class.
+  virtual const TargetRegisterClass *
     getISARegClass(const TargetRegisterClass * rc) const;
 
-    unsigned getHWRegNum(unsigned reg) const;
+  /// getHWRegNum - Generated function that returns the hardware encoding for
+  /// a register
+  unsigned getHWRegNum(unsigned reg) const;
 
-  };
+  /// getCFGStructurizerRegClass - get the register class of the specified
+  /// type to use in the CFGStructurizer
+  virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
+
+};
 
 } // End namespace llvm