#include "r600_cs.h"
/* 2xMSAA
- * There are two locations (-4, 4), (4, -4). */
+ * There are two locations (4, 4), (-4, -4). */
const uint32_t eg_sample_locs_2x[4] = {
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
- FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
+ FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
+ FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
+ FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
+ FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
};
const unsigned eg_max_dist_2x = 4;
/* 4xMSAA
- * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
+ * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
const uint32_t eg_sample_locs_4x[4] = {
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
- FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
+ FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
+ FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
+ FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
+ FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
};
const unsigned eg_max_dist_4x = 6;
/* Cayman 8xMSAA */
static const uint32_t cm_sample_locs_8x[] = {
- FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
- FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
- FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
- FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
- FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
- FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
- FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
- FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
+ FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
+ FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
+ FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
+ FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
+ FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
+ FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
+ FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
+ FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
};
static const unsigned cm_max_dist_8x = 8;
/* Cayman 16xMSAA */
static const uint32_t cm_sample_locs_16x[] = {
- FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
- FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
- FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
- FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
- FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
- FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
- FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
- FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
- FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
- FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
- FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
- FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
- FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
- FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
- FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
- FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
+ FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
+ FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
+ FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
+ FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
+ FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
+ FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
+ FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
+ FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
+ FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
+ FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
+ FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
+ FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
+ FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
+ FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
+ FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
+ FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
};
static const unsigned cm_max_dist_16x = 8;
}
}
-void cayman_emit_msaa_state(struct radeon_winsys_cs *cs, int nr_samples)
+void cayman_init_msaa(struct pipe_context *ctx)
{
- unsigned max_dist = 0;
+ struct r600_common_context *rctx = (struct r600_common_context*)ctx;
+ int i;
+ cayman_get_sample_position(ctx, 1, 0, rctx->sample_locations_1x[0]);
+
+ for (i = 0; i < 2; i++)
+ cayman_get_sample_position(ctx, 2, i, rctx->sample_locations_2x[i]);
+ for (i = 0; i < 4; i++)
+ cayman_get_sample_position(ctx, 4, i, rctx->sample_locations_4x[i]);
+ for (i = 0; i < 8; i++)
+ cayman_get_sample_position(ctx, 8, i, rctx->sample_locations_8x[i]);
+ for (i = 0; i < 16; i++)
+ cayman_get_sample_position(ctx, 16, i, rctx->sample_locations_16x[i]);
+}
+
+void cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples)
+{
switch (nr_samples) {
default:
- nr_samples = 0;
+ case 1:
+ radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
+ radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
+ radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
+ radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
break;
case 2:
- r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
- r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
- r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
- r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
- max_dist = eg_max_dist_2x;
+ radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
+ radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
+ radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
+ radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
break;
case 4:
- r600_write_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
- r600_write_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
- r600_write_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
- r600_write_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
- max_dist = eg_max_dist_4x;
+ radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
+ radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
+ radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
+ radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
break;
case 8:
- r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
+ radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
radeon_emit(cs, cm_sample_locs_8x[0]);
radeon_emit(cs, cm_sample_locs_8x[4]);
radeon_emit(cs, 0);
radeon_emit(cs, 0);
radeon_emit(cs, cm_sample_locs_8x[3]);
radeon_emit(cs, cm_sample_locs_8x[7]);
- max_dist = cm_max_dist_8x;
break;
case 16:
- r600_write_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
+ radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
radeon_emit(cs, cm_sample_locs_16x[0]);
radeon_emit(cs, cm_sample_locs_16x[4]);
radeon_emit(cs, cm_sample_locs_16x[8]);
radeon_emit(cs, cm_sample_locs_16x[7]);
radeon_emit(cs, cm_sample_locs_16x[11]);
radeon_emit(cs, cm_sample_locs_16x[15]);
- max_dist = cm_max_dist_16x;
break;
}
+}
+
+void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
+ int ps_iter_samples, int overrast_samples,
+ unsigned sc_mode_cntl_1)
+{
+ int setup_samples = nr_samples > 1 ? nr_samples :
+ overrast_samples > 1 ? overrast_samples : 0;
+ /* Required by OpenGL line rasterization.
+ *
+ * TODO: We should also enable perpendicular endcaps for AA lines,
+ * but that requires implementing line stippling in the pixel
+ * shader. SC can only do line stippling with axis-aligned
+ * endcaps.
+ */
+ unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
- if (nr_samples > 1) {
- unsigned log_samples = util_logbase2(nr_samples);
+ if (setup_samples > 1) {
+ /* indexed by log2(nr_samples) */
+ unsigned max_dist[] = {
+ 0,
+ eg_max_dist_2x,
+ eg_max_dist_4x,
+ cm_max_dist_8x,
+ cm_max_dist_16x
+ };
+ unsigned log_samples = util_logbase2(setup_samples);
+ unsigned log_ps_iter_samples =
+ util_logbase2(util_next_power_of_two(ps_iter_samples));
- r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
- radeon_emit(cs, S_028BDC_LAST_PIXEL(1) |
+ radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
+ radeon_emit(cs, sc_line_cntl |
S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
- S_028BE0_MAX_SAMPLE_DIST(max_dist) |
+ S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
- r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
- S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
- S_028804_PS_ITER_SAMPLES(log_samples) |
- S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
- S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
- S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
- S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
+ if (nr_samples > 1) {
+ radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
+ S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
+ S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
+ S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
+ S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
+ S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
+ S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
+ radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
+ EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
+ sc_mode_cntl_1);
+ } else if (overrast_samples > 1) {
+ radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
+ S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
+ S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
+ S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
+ radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
+ sc_mode_cntl_1);
+ }
} else {
- r600_write_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
- radeon_emit(cs, S_028BDC_LAST_PIXEL(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
+ radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
+ radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
- r600_write_context_reg(cs, CM_R_028804_DB_EQAA,
+ radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
+ radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
+ sc_mode_cntl_1);
}
}
projects / mesa.git / blobdiff